Input Parameters Specification
Divider Resistors (R1, R2, R3)The three-resistor base divider network setting up stable base bias voltages for both transistor stages.
Collector Resistor (RC)The load resistor connected between the collector of the top transistor and positive supply rail.
Emitter Resistors (RE1, RE2)RE1 is AC-bypassed by CE1 to maximize gain, while RE2 is unbypassed to stabilize feedback and control overall gain.
Parasitics & Transition (Ft, Ccb, Cbe)The transit frequency (Ft) and internal depletion capacitance parameters limiting high-frequency bandwidth.
Practical Operational Examples
UHF RF Preamplifier
R1 = R2 = R3 = 10 kΩ, RC = 1.2 kΩ
RE1 = 0.5 kΩ, RE2 = 50 Ω, VP = 12 V
Beta = 100, RS = 50 Ω, RL = 1.0 kΩ
Computed High Frequency Bounds
• Transconductance gm = 138 mS
• System Bandwidth BW = 38.6 MHz
• Mitigates parasitic Miller multiplication effects.
Diagrams & Theory
A Cascode Amplifier stacks a Common-Emitter (CE) input stage with a Common-Base (CB) output stage. This prevents the collector voltage of the input stage from fluctuating, eliminating the Miller capacitance multiplication effect and significantly extending high-frequency bandwidth.
The cascode topology consists of an NPN Common-Emitter input stage (Q1) driving an NPN Common-Base output stage (Q2). Since the collector of Q1 is held at a relatively constant potential (VE2), its dynamic voltage swing is minimal, practically eliminating Miller capacitance multiplication and greatly boosting overall system bandwidth.
Formulas & Mathematical Logic
Base Bias 1: VB1 = VP * R3 / (R1 + R2 + R3)
Base Bias 2: VB2 = VP * (R2 + R3) / (R1 + R2 + R3)
Operating Currents: IB = (VB1 - VBE) / (RB1 + Beta * RE12)
Voltage Gain (A1): A1 = -gm * RLC * R23 / (R23 + RS) * Rpi / (Rpi + Rx + R23S)
Voltage Gain (A2): A2 = -RLC / RE2
Cutoff Frequency (f1): f1 = 1 / (2 * pi * Rs_p * (Cbe + 2 * Ccb))
These equations evaluate both DC biasing thresholds and high-frequency AC behaviors. It calculates the resulting bandwidth limits based on the dominant poles of the input and output nodes.
Step-by-Step Example
Example: Configuring a cascode block with R1 = 10k, R2 = 10k, R3 = 10k, RC = 1.2k, RE1 = 0.5k, RE2 = 50 ohms, and VP = 12V.
Step 1: Calculate the base divider voltages: VB1 = 12 * 10k / 30k = 4.0V, VB2 = 12 * 20k / 30k = 8.0V.
Step 2: Establish base current IB and collector current IC using the unbypassed feedback resistance.
Step 3: Resolve BJT transconductance: gm = IC / 0.025.
Step 4: Solve the separate gain limits A1 and A2, matching the dominant value as the overall gain.
Step 5: Determine the individual cutoff poles (f1 and f2) to resolve total bandwidth (BW).
How to Use This Calculator
Enter your divider resistances R1, R2, and R3 in k-ohms (kΩ).
Specify the load, emitter feedback, and collector resistor parameters.
Input BJT datasheet properties (Beta gain, forward VBE, and transition frequencies).
Click Calculate to evaluate overall voltages, currents, transconductance, input impedances, gain, and system bandwidth.
About This Calculator
Model, analyze, and optimize BJT Cascode configurations to mitigate Miller effect limits with CalcBoy's professional suite.
This design tool evaluates DC biasing operating points, AC input resistances, voltage gain, and high-frequency bandwidth constraints.
In high-frequency RF and wideband analog signal amplification, standard common-emitter BJT stages suffer from severe bandwidth limitations due to the Miller effect. When a common-emitter amplifier exhibits high voltage gain, the parasitic collector-base capacitance (Ccb or Cu) is multiplied by the voltage gain of the stage. This creates a massive equivalent input capacitance that acts as a low-pass filter with the source resistance, heavily restricting high-frequency bandwidth [6].
To overcome this, engineers utilize a two-stage cascode topology. In a BJT cascode, a common-emitter input stage (Q1) is stacked in series with a common-base output stage (Q2). Q1 acts as a transconductance amplifier, feeding its output current directly into the low-input-impedance emitter of Q2 [6]. Because the emitter of Q2 presents an extremely low impedance, the voltage swing at the collector of Q1 is near zero [6]. With virtually no voltage gain in the input stage, the Miller multiplication effect is completely eliminated, extending the upper cutoff frequency boundary significantly [6].
This calculator processes these complex high-frequency poles and DC biasing constraints systematically. By inputting resistor configurations, supply levels, and BJT datasheet parasitics, the tool calculates transconductance, input impedances, voltage gains, and system bandwidth (BW), allowing engineers to quickly optimize wideband receiver preamplifiers before prototyping [6].
Typical ApplicationsWideband RF preamplifiers, high-frequency oscilloscope inputs, tuner stages, and low-noise receivers.
Calculated DeliverablesBias voltages (VB, VE, VC), operating currents, input impedances, gain limits, and bandwidth.
Target AudienceRF hardware designers, telecommunications engineers, and advanced electronics students.
Thermal PracticeUse identical transistor packages for Q1 and Q2 to ensure matched thermal drift behaviors across active bias regions.
Tip: Always bypass the base of the upper common-base transistor (Q2) with a high-quality ceramic capacitor (C1) close to the BJT pin to ensure a solid high-frequency AC ground path [6].
Frequently Asked Questions
1. What is a cascode amplifier and how does it prevent the Miller effect?
A cascode amplifier stacks a common-emitter stage (Q1) in series with a common-base stage (Q2). Since the common-base emitter offers a very low input impedance, the collector of Q1 experiences almost no voltage swing. Eliminating this voltage swing prevents the feedback capacitance (Ccb) from multiplying, mitigating the Miller effect.
2. What is the role of R1, R2, and R3 in the biasing network?
This three-resistor voltage divider establishes the stable base bias voltages for both Q1 and Q2 from a single power supply, keeping both active BJTs biased in their linear operating regions.
3. Why are there two separate emitter resistors (RE1 and RE2) in the schematic?
RE1 is bypassed by capacitor CE1 to maximize AC voltage gain, while RE2 remains unbypassed. RE2 provides local negative feedback to control the overall gain, stabilize the bias point, and linearize the amplifier's input stage.
4. How is the transition frequency (Ft) related to the BJT's bandwidth?
The transition frequency (Ft) is the gain-bandwidth product where the BJT's current gain drops to unity. It defines the absolute upper physics-based speed limit of the transistor itself, which bounds the maximum achievable amplifier bandwidth.
5. Can I use this calculator for other transistor types like MOSFETs?
While the cascode concept is identical for FETs, this specific calculator is mathematically modeled around Bipolar Junction Transistors (BJTs), incorporating base currents, VBE drops, and hFE/Beta current gain variables.
6. Why is a bypass capacitor (C1) needed at the base of the upper transistor Q2?
The upper transistor (Q2) operates as a common-base stage. For proper common-base operation, the base must be at a solid AC ground. The bypass capacitor C1 shunts any high-frequency AC signals at the base of Q2 directly to ground.