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An IC or chip pinout database is a technical reference guide that provides physical pin configurations, functional descriptions, and schematic diagrams for integrated circuits (ICs), microcontrollers, and transistors.

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16550 - Universal asynchronous receiver-transmitter with FIFOs - msarnoff.org ChipDB

16550

Universal asynchronous receiver-transmitter with FIFOs


D₀	1 •	40	Vcc
D₁	2	39	RI
D₂	3	38	DCD
D₃	4	37	DSR
D₄	5	36	CTS
D₅	6	35	MR
D₆	7	34	OUT1
D₇	8	33	DTR
RCLK	9	32	RTS
RX	10	31	OUT2
TX	11	30	INTR
CS0	12	29	RXRDY
CS1	13	28	A₀
CS2	14	27	A₁
BAUDOUT	15	26	A₂
XIN	16	25	ADS
XOUT	17	24	TXRDY
WR	18	23	DDIS
WR	19	22	RD
GND	20	21	RD

Pin	Symbol	Description
1	D₀	data bus
2	D₁	data bus
3	D₂	data bus
4	D₃	data bus
5	D₄	data bus
6	D₅	data bus
7	D₆	data bus
8	D₇	data bus
9	RCLK	receiver clock input (16x baud rate)
10	RX	serial input
11	TX	serial output
12	CS0	chip select (active high)
13	CS1	chip select (active high)
14	CS2	chip select (active low)
15	BAUDOUT	baud rate generator output
16	XIN	external crystal input
17	XOUT	external crystal output
18	WR	write enable (active low)
19	WR	write enable (active high)
20	GND	ground
21	RD	read enable (active low)
22	RD	read enable (active high)
23	DDIS	driver disable
24	TXRDY	TX DMA signal
25	ADS	address strobe input
26	A₂	register select
27	A₁	register select
28	A₀	register select
29	RXRDY	RX DMA signal
30	INTR	interrupt output (active high)
31	OUT2	general purpose output
32	RTS	request to send (output to modem)
33	DTR	data terminal ready (output to modem)
34	OUT1	general purpose output
35	MR	master reset (active high)
36	CTS	clear to send (input from modem)
37	DSR	data set ready (input from modem)
38	DCD	data carrier detect (input from modem)
39	RI	ring indicator (input from modem)
40	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
maximum baud rate	1.5	Mbaud

Notes

When bit 7 in the Line Control Register is set, the baud rate divisor latch is enabled. (register 000=LSB, register 001=MSB)

16550 - Universal asynchronous receiver-transmitter with FIFOs - msarnoff.org ChipDB

16550

Universal asynchronous receiver-transmitter with FIFOs


D₀	1 •	40	Vcc
D₁	2	39	RI
D₂	3	38	DCD
D₃	4	37	DSR
D₄	5	36	CTS
D₅	6	35	MR
D₆	7	34	OUT1
D₇	8	33	DTR
RCLK	9	32	RTS
RX	10	31	OUT2
TX	11	30	INTR
CS0	12	29	RXRDY
CS1	13	28	A₀
CS2	14	27	A₁
BAUDOUT	15	26	A₂
XIN	16	25	ADS
XOUT	17	24	TXRDY
WR	18	23	DDIS
WR	19	22	RD
GND	20	21	RD

Pin	Symbol	Description
1	D₀	data bus
2	D₁	data bus
3	D₂	data bus
4	D₃	data bus
5	D₄	data bus
6	D₅	data bus
7	D₆	data bus
8	D₇	data bus
9	RCLK	receiver clock input (16x baud rate)
10	RX	serial input
11	TX	serial output
12	CS0	chip select (active high)
13	CS1	chip select (active high)
14	CS2	chip select (active low)
15	BAUDOUT	baud rate generator output
16	XIN	external crystal input
17	XOUT	external crystal output
18	WR	write enable (active low)
19	WR	write enable (active high)
20	GND	ground
21	RD	read enable (active low)
22	RD	read enable (active high)
23	DDIS	driver disable
24	TXRDY	TX DMA signal
25	ADS	address strobe input
26	A₂	register select
27	A₁	register select
28	A₀	register select
29	RXRDY	RX DMA signal
30	INTR	interrupt output (active high)
31	OUT2	general purpose output
32	RTS	request to send (output to modem)
33	DTR	data terminal ready (output to modem)
34	OUT1	general purpose output
35	MR	master reset (active high)
36	CTS	clear to send (input from modem)
37	DSR	data set ready (input from modem)
38	DCD	data carrier detect (input from modem)
39	RI	ring indicator (input from modem)
40	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
maximum baud rate	1.5	Mbaud

Notes

When bit 7 in the Line Control Register is set, the baud rate divisor latch is enabled. (register 000=LSB, register 001=MSB)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

1802 - CDP1802 CMOS 8-bit microprocessor - msarnoff.org ChipDB

1802

CDP1802 CMOS 8-bit microprocessor


CLOCK	1 •	40	V_DD
WAIT	2	39	XTAL
CLEAR	3	38	DMA_IN
Q	4	37	DMA_OUT
SC1	5	36	INTERRUPT
SC0	6	35	MWR
MRD	7	34	TPA
BUS 7	8	33	TPB
BUS 6	9	32	MA7
BUS 5	10	31	MA6
BUS 4	11	30	MA5
BUS 3	12	29	MA4
BUS 2	13	28	MA3
BUS 1	14	27	MA2
BUS 0	15	26	MA1
V_CC	16	25	MA0
N2	17	24	EF1
N1	18	23	EF2
N0	19	22	EF3
V_SS	20	21	EF4

Pin	Symbol	Description
1	CLOCK	input for externally generated single-phase clock
2	WAIT	control line
3	CLEAR	control line
4	Q	general output
5	SC1	state code
6	SC0	state code
7	MRD	read pulse
8	BUS 7	data bus
9	BUS 6	data bus
10	BUS 5	data bus
11	BUS 4	data bus
12	BUS 3	data bus
13	BUS 2	data bus
14	BUS 1	data bus
15	BUS 0	data bus
16	V_CC	I/O voltage supply
17	N2	I/O control line
18	N1	I/O control line
19	N0	I/O control line
20	V_SS	ground
21	EF4	I/O flag
22	EF3	I/O flag
23	EF2	I/O flag
24	EF1	I/O flag
25	MA0	memory address
26	MA1	memory address
27	MA2	memory address
28	MA3	memory address
29	MA4	memory address
30	MA5	memory address
31	MA6	memory address
32	MA7	memory address
33	TPB	timing pulse
34	TPA	timing pulse
35	MWR	write pulse
36	INTERRUPT	interrupt
37	DMA_OUT	DMA out
38	DMA_IN	DMA in
39	XTAL	crystal input, for on-chip oscillator
40	V_DD	internal voltage supply

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum input clock maximum frequency at 5V	3.2	MHz
Maximum input clock maximum frequency at 10V	6.4	MHz
Minimum instruction fetch-execute time at 5V	5.0	µs

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

24LC256 - 256K I2C CMOS serial EEPROM - msarnoff.org ChipDB

24LC256

256K I2C CMOS serial EEPROM


A0	1 •	8	Vcc
A1	2	7	WP
A2	3	6	SCL
GND	4	5	SDA

Pin	Symbol	Description
1	A0	user-configurable chip select
2	A1	user-configurable chip select
3	A2	user-configurable chip select
4	GND	ground
5	SDA	serial data input/output
6	SCL	serial clock input
7	WP	write protect (active high)
8	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Minimum supply voltage	1.7 (24AA256) 2.5 (24LC256) 1.7 (24FC256)	V
Maximum clock frequency	100k (Vcc < 2.5V) 400k (24AA256) 400k (24LC256) 1M (24FC256)	Hz
Maximum write cycle time	5	ms
Endurance	1 000 000	cycles

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

24LC256 - 256K I2C CMOS serial EEPROM - msarnoff.org ChipDB

24LC256

256K I2C CMOS serial EEPROM


A0	1 •	8	Vcc
A1	2	7	WP
A2	3	6	SCL
GND	4	5	SDA

Pin	Symbol	Description
1	A0	user-configurable chip select
2	A1	user-configurable chip select
3	A2	user-configurable chip select
4	GND	ground
5	SDA	serial data input/output
6	SCL	serial clock input
7	WP	write protect (active high)
8	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Minimum supply voltage	1.7 (24AA256) 2.5 (24LC256) 1.7 (24FC256)	V
Maximum clock frequency	100k (Vcc < 2.5V) 400k (24AA256) 400k (24LC256) 1M (24FC256)	Hz
Maximum write cycle time	5	ms
Endurance	1 000 000	cycles

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

24LC256 - 256K I2C CMOS serial EEPROM - msarnoff.org ChipDB

24LC256

256K I2C CMOS serial EEPROM


A0	1 •	8	Vcc
A1	2	7	WP
A2	3	6	SCL
GND	4	5	SDA

Pin	Symbol	Description
1	A0	user-configurable chip select
2	A1	user-configurable chip select
3	A2	user-configurable chip select
4	GND	ground
5	SDA	serial data input/output
6	SCL	serial clock input
7	WP	write protect (active high)
8	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Minimum supply voltage	1.7 (24AA256) 2.5 (24LC256) 1.7 (24FC256)	V
Maximum clock frequency	100k (Vcc < 2.5V) 400k (24AA256) 400k (24LC256) 1M (24FC256)	Hz
Maximum write cycle time	5	ms
Endurance	1 000 000	cycles

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

28C64 - 8K x 8 parallel EEPROM - msarnoff.org ChipDB

28C64

8K x 8 parallel EEPROM


RDY/BUSY	1 •	28	Vcc
A₁₂	2	27	WE
A₇	3	26	NC
A₆	4	25	A₈
A₅	5	24	A₉
A₄	6	23	A₁₁
A₃	7	22	OE
A₂	8	21	A₁₀
A₁	9	20	CE
A₀	10	19	I/O₇
I/O₀	11	18	I/O₆
I/O₁	12	17	I/O₅
I/O₂	13	16	I/O₄
GND	14	15	I/O₃

Pin	Symbol	Description
1	RDY/BUSY	device status
2	A₁₂	address input
3	A₇	address input
4	A₆	address input
5	A₅	address input
6	A₄	address input
7	A₃	address input
8	A₂	address input
9	A₁	address input
10	A₀	address input
11	I/O₀	data input/output
12	I/O₁	data input/output
13	I/O₂	data input/output
14	GND	ground
15	I/O₃	data input/output
16	I/O₄	data input/output
17	I/O₅	data input/output
18	I/O₆	data input/output
19	I/O₇	data input/output
20	CE	chip enable (active low)
21	A₁₀	address input
22	OE	output enable (active low)
23	A₁₁	address input
24	A₉	address input
25	A₈	address input
26	NC	no connection
27	WE	write enable (active low)
28	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4001 - Quad 2-input NOR gate - msarnoff.org ChipDB

4001

Quad 2-input NOR gate


1A	1 •	14	Vcc
1B	2	13	4B
1Y	3	12	4A
2Y	4	11	4Y
2A	5	10	3Y
2B	6	9	3B
GND	7	8	3A

Pin	Symbol	Description
1	1A	data input
2	1B	data input
3	1Y	data output
4	2Y	data output
5	2A	data input
6	2B	data input
7	GND	ground
8	3A	data input
9	3B	data input
10	3Y	data output
11	4Y	data output
12	4A	data input
13	4B	data input
14	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4002 - Dual 4-input NOR gate - msarnoff.org ChipDB

4002

Dual 4-input NOR gate


1Y	1 •	14	Vcc
1A	2	13	2Y
1B	3	12	2D
1C	4	11	2C
1D	5	10	2B
NC	6	9	2A
GND	7	8	NC

Pin	Symbol	Description
1	1Y	data output
2	1A	data input
3	1B	data input
4	1C	data input
5	1D	data input
6	NC	no connection
7	GND	ground
8	NC	no connection
9	2A	data input
10	2B	data input
11	2C	data input
12	2D	data input
13	2Y	data output
14	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4011 - Quad 2-input NAND gate - msarnoff.org ChipDB

4011

Quad 2-input NAND gate


1A	1 •	14	Vcc
1B	2	13	4B
1Y	3	12	4A
2Y	4	11	4Y
2A	5	10	3Y
2B	6	9	3B
GND	7	8	3A

Pin	Symbol	Description
1	1A	data input
2	1B	data input
3	1Y	data output
4	2Y	data output
5	2A	data input
6	2B	data input
7	GND	ground
8	3A	data input
9	3B	data input
10	3Y	data output
11	4Y	data output
12	4A	data input
13	4B	data input
14	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4013 - Dual D-type flip-flop with set and clear - msarnoff.org ChipDB

4013

Dual D-type flip-flop with set and clear


1Q	1 •	14	Vcc
1Q	2	13	2Q
1CP	3	12	2Q
1CD	4	11	2CP
1D	5	10	2CD
1SD	6	9	2D
GND	7	8	2SD

Pin	Symbol	Description
1	1Q	true output
2	1Q	complement output
3	1CP	clock input (low-to-high edge-triggered)
4	1CD	asynchronous clear-direct input
5	1D	data input
6	1SD	asynchronous set-direct input
7	GND	ground
8	2SD	asynchronous set-direct input
9	2D	data input
10	2CD	asynchronous clear-direct input
11	2CP	clock input (low-to-high edge-triggered)
12	2Q	complement output
13	2Q	true output
14	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4014 - 8-bit static shift register - msarnoff.org ChipDB

4014

8-bit static shift register


D7	1 •	16	Vcc
Q5	2	15	D6
Q7	3	14	D5
D3	4	13	D4
D2	5	12	Q6
D1	6	11	DS
D0	7	10	CP
GND	8	9	PE

Pin	Symbol	Description
1	D7	parallel data input
2	Q5	output
3	Q7	output
4	D3	parallel data input
5	D2	parallel data input
6	D1	parallel data input
7	D0	parallel data input
8	GND	ground
9	PE	parallel enable input
10	CP	clock input (low-to-high edge-triggered)
11	DS	serial data input
12	Q6	output
13	D4	parallel data input
14	D5	parallel data input
15	D6	parallel data input
16	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4015 - Dual 4-bit serial-in/parallel-out shift register - msarnoff.org ChipDB

4015

Dual 4-bit serial-in/parallel-out shift register


2CP	1 •	16	Vcc
2Q3	2	15	2D
1Q2	3	14	2MR
1Q1	4	13	2Q0
1Q0	5	12	2Q1
1MR	6	11	2Q2
1D	7	10	1Q3
GND	8	9	1CP

Pin	Symbol	Description
1	2CP	clock input (low-to-high edge-triggered)
2	2Q3	parallel output
3	1Q2	parallel output
4	1Q1	parallel output
5	1Q0	parallel output
6	1MR	master reset
7	1D	serial data input
8	GND	ground
9	1CP	clock input (low-to-high edge-triggered)
10	1Q3	parallel output
11	2Q2	parallel output
12	2Q1	parallel output
13	2Q0	parallel output
14	2MR	master reset
15	2D	serial data input
16	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4017 - Decade counter/divider with 10 decoded outputs - msarnoff.org ChipDB

4017

Decade counter/divider with 10 decoded outputs


Q5	1 •	16	Vcc
Q1	2	15	RESET
Q0	3	14	CLOCK
Q2	4	13	CE
Q6	5	12	CARRY
Q7	6	11	Q9
Q3	7	10	Q4
GND	8	9	Q8

Pin	Symbol	Description
1	Q5	output
2	Q1	output
3	Q0	output
4	Q2	output
5	Q6	output
6	Q7	output
7	Q3	output
8	GND	ground
9	Q8	output
10	Q4	output
11	Q9	output
12	CARRY	carry output
13	CE	clock enable (active low)
14	CLOCK	clock input (low-to-high, positive edge triggered)
15	RESET	reset (active high)
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum clock frequency	2 (CD4017) 77 (74HC4017)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4020 - 14-stage binary counter - msarnoff.org ChipDB

4020

14-stage binary counter


Q11	1 •	16	Vcc
Q12	2	15	Q10
Q13	3	14	Q9
Q5	4	13	Q7
Q4	5	12	Q8
Q6	6	11	MR
Q3	7	10	CP
GND	8	9	Q0

Pin	Symbol	Description
1	Q11	output
2	Q12	output
3	Q13	output
4	Q5	output
5	Q4	output
6	Q6	output
7	Q3	output
8	GND	ground
9	Q0	output
10	CP	clock input (high-to-low edge-triggered)
11	MR	master reset
12	Q8	output
13	Q7	output
14	Q9	output
15	Q10	output
16	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4021 - 8-bit static shift register - msarnoff.org ChipDB

4021

8-bit static shift register


D7	1 •	16	Vcc
Q5	2	15	D6
Q7	3	14	D5
D3	4	13	D4
D2	5	12	Q6
D1	6	11	DS
D0	7	10	CP
GND	8	9	PL

Pin	Symbol	Description
1	D7	parallel data input
2	Q5	output
3	Q7	output
4	D3	parallel data input
5	D2	parallel data input
6	D1	parallel data input
7	D0	parallel data input
8	GND	ground
9	PL	parallel load
10	CP	clock input (low-to-high edge-triggered)
11	DS	serial data input
12	Q6	output
13	D4	parallel data input
14	D5	parallel data input
15	D6	parallel data input
16	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4023 - Triple 3-input NAND gate - msarnoff.org ChipDB

4023

Triple 3-input NAND gate


2A	1 •	14	Vcc
2B	2	13	3C
1A	3	12	3B
1B	4	11	3A
1C	5	10	3Y
1Y	6	9	2Y
GND	7	8	2C

Pin	Symbol	Description
1	2A	data input
2	2B	data input
3	1A	data input
4	1B	data input
5	1C	data input
6	1Y	data output
7	GND	ground
8	2C	data input
9	2Y	data output
10	3Y	data output
11	3A	data input
12	3B	data input
13	3C	data input
14	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4024 - 7-stage binary ripple counter - msarnoff.org ChipDB

4024

7-stage binary ripple counter


CP	1 •	14	Vcc
MR	2	13	NC
Q6	3	12	Q0
Q5	4	11	Q1
Q4	5	10	NC
Q3	6	9	Q2
GND	7	8	NC

Pin	Symbol	Description
1	CP	clock input (high-to-low edge-triggered)
2	MR	master reset
3	Q6	buffered parallel output
4	Q5	buffered parallel output
5	Q4	buffered parallel output
6	Q3	buffered parallel output
7	GND	ground
8	NC	no connection
9	Q2	buffered parallel output
10	NC	no connection
11	Q1	buffered parallel output
12	Q0	buffered parallel output
13	NC	no connection
14	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4025 - Triple 3-input NOR gate - msarnoff.org ChipDB

4025

Triple 3-input NOR gate


2A	1 •	14	Vcc
2B	2	13	3C
1A	3	12	3B
1B	4	11	3A
1C	5	10	3Y
1Y	6	9	2Y
GND	7	8	2C

Pin	Symbol	Description
1	2A	data input
2	2B	data input
3	1A	data input
4	1B	data input
5	1C	data input
6	1Y	data output
7	GND	ground
8	2C	data input
9	2Y	data output
10	3Y	data output
11	3A	data input
12	3B	data input
13	3C	data input
14	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4027 - Dual J-K flip-flop with set and clear - msarnoff.org ChipDB

4027

Dual J-K flip-flop with set and clear


2Q	1 •	16	Vcc
2Q	2	15	1Q
2CP	3	14	1Q
2CD	4	13	1CP
2K	5	12	1CD
2J	6	11	1K
2SD	7	10	1J
GND	8	9	1SD

Pin	Symbol	Description
1	2Q	true output
2	2Q	complement output
3	2CP	clock input (low-to-high edge-triggered)
4	2CD	asynchronous clear-direct input
5	2K	synchronous input
6	2J	synchronous input
7	2SD	asynchronous set-direct input
8	GND	ground
9	1SD	asynchronous set-direct input
10	1J	asynchronous input
11	1K	asynchronous input
12	1CD	asynchronous clear-direct input
13	1CP	clock input (low-to-high edge-triggered)
14	1Q	complement output
15	1Q	true output
16	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4028 - BCD to decimal decoder - msarnoff.org ChipDB
4028
BCD to decimal decoder

Y4 1 • 16 Vcc
Y2 2 15 Y3
Y0 3 14 Y1
Y7 4 13 A1
Y9 5 12 A2
Y5 6 11 A3
Y6 7 10 A0
GND 8 9 Y8

Pin Symbol Description
1 Y4 output
2 Y2 output
3 Y0 output
4 Y7 output
5 Y9 output
6 Y5 output
7 Y6 output
8 GND ground
9 Y8 output
10 A0 BCD input
11 A3 BCD input
12 A2 BCD input
13 A1 BCD input
14 Y1 output
15 Y3 output
16 Vcc supply voltage

Notes
Outputs are active high.All outputs are low for BCD inputs greater than 9.
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

Pin	Symbol	Description
1	Y4	output
2	Y2	output
3	Y0	output
4	Y7	output
5	Y9	output
6	Y5	output
7	Y6	output
8	GND	ground
9	Y8	output
10	A0	BCD input
11	A3	BCD input
12	A2	BCD input
13	A1	BCD input
14	Y1	output
15	Y3	output
16	Vcc	supply voltage

4029 - Synchronous 4-bit up/down binary/decade counter - msarnoff.org ChipDB

4029

Synchronous 4-bit up/down binary/decade counter


PL	1 •	16	Vcc
Q3	2	15	CP
P3	3	14	Q2
P0	4	13	P2
CE	5	12	P1
Q0	6	11	Q1
TC	7	10	UP/DN
GND	8	9	BIN/DEC

Pin	Symbol	Description
1	PL	parallel load
2	Q3	buffered parallel output
3	P3	parallel data input
4	P0	parallel data input
5	CE	count enable (active low)
6	Q0	buffered parallel output
7	TC	terminal count output (active low)
8	GND	ground
9	BIN/DEC	binary/decade control input
10	UP/DN	up/down control input
11	Q1	buffered parallel output
12	P1	parallel data input
13	P2	parallel data input
14	Q2	buffered parallel output
15	CP	clock input (low-to-high edge-triggered)
16	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4030 - Quad 2-input XOR gate - msarnoff.org ChipDB

4030

Quad 2-input XOR gate


1A	1 •	14	Vcc
1B	2	13	4B
1Y	3	12	4A
2Y	4	11	4Y
2A	5	10	3Y
2B	6	9	3B
GND	7	8	3A

Pin	Symbol	Description
1	1A	data input
2	1B	data input
3	1Y	data output
4	2Y	data output
5	2A	data input
6	2B	data input
7	GND	ground
8	3A	data input
9	3B	data input
10	3Y	data output
11	4Y	data output
12	4A	data input
13	4B	data input
14	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4040 - 12-stage binary ripple counter - msarnoff.org ChipDB

4040

12-stage binary ripple counter


Q11	1 •	16	Vcc
Q5	2	15	Q10
Q4	3	14	Q9
Q6	4	13	Q7
Q3	5	12	Q8
Q2	6	11	MR
Q1	7	10	CP
GND	8	9	Q0

Pin	Symbol	Description
1	Q11	output
2	Q5	output
3	Q4	output
4	Q6	output
5	Q3	output
6	Q2	output
7	Q1	output
8	GND	ground
9	Q0	output
10	CP	clock input (high-to-low edge-triggered)
11	MR	master reset (active high)
12	Q8	output
13	Q7	output
14	Q9	output
15	Q10	output
16	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4046 - Phase-locked loop - msarnoff.org ChipDB

4046

Phase-locked loop


PCP_OUT	1 •	16	Vcc
PC1_OUT	2	15	ZENER
COMP_IN	3	14	SIGN_IN
VCO_OUT	4	13	PC2_OUT
INH	5	12	R₂
C1_A	6	11	R₁
C1_B	7	10	SF_OUT
GND	8	9	VCO_IN

Pin	Symbol	Description
1	PCP_OUT	phase comparator pulse output
2	PC1_OUT	phase comparator 1 output
3	COMP_IN	comparator input
4	VCO_OUT	VCO output
5	INH	inhibit
6	C1_A	capacitor C1 connection A
7	C1_B	capacitor C1 Connection B
8	GND	ground
9	VCO_IN	VCO input
10	SF_OUT	source-follower output
11	R₁	resistor R1 connection
12	R₂	resistor R2 connection
13	PC2_OUT	phase comparator 2 output
14	SIGN_IN	signal input
15	ZENER	zener diode input for regulated supply
16	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4047 - Monostable/astable multivibrator - msarnoff.org ChipDB

4047

Monostable/astable multivibrator


C	1 •	14	Vcc
R	2	13	OSC OUT
RC COMMON	3	12	RETRIGGER
ASTABLE	4	11	Q
ASTABLE	5	10	Q
-TRIGGER	6	9	RESET
GND	7	8	+TRIGGER

Pin	Symbol	Description
1	C	capacitor connection
2	R	resistor connection
3	RC COMMON	resistor and capacitor common connection
4	ASTABLE	astable enable (active low)
5	ASTABLE	astable enable (active high)
6	-TRIGGER	monostable negative-edge trigger
7	GND	ground
8	+TRIGGER	monostable positive-edge trigger
9	RESET	external reset
10	Q	output
11	Q	complement output
12	RETRIGGER	monostable retrigger input
13	OSC OUT	oscillator (double frequency) output
14	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4049 - Hex inverting buffer - msarnoff.org ChipDB

4049

Hex inverting buffer


Vcc	1 •	16	NC
1Y	2	15	6Y
1A	3	14	6A
2Y	4	13	NC
2A	5	12	5Y
3Y	6	11	5A
3A	7	10	4Y
GND	8	9	4A

Pin	Symbol	Description
1	Vcc	supply voltage
2	1Y	data output
3	1A	data input
4	2Y	data output
5	2A	data input
6	3Y	data output
7	3A	data input
8	GND	ground
9	4A	data input
10	4Y	data output
11	5A	data input
12	5Y	data output
13	NC	no connection
14	6A	data input
15	6Y	data output
16	NC	no connection

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4050 - Hex non-inverting buffer - msarnoff.org ChipDB

4050

Hex non-inverting buffer


Vcc	1 •	16	NC
1Y	2	15	6Y
1A	3	14	6A
2Y	4	13	NC
2A	5	12	5Y
3Y	6	11	5A
3A	7	10	4Y
GND	8	9	4A

Pin	Symbol	Description
1	Vcc	supply voltage
2	1Y	data output
3	1A	data input
4	2Y	data output
5	2A	data input
6	3Y	data output
7	3A	data input
8	GND	ground
9	4A	data input
10	4Y	data output
11	5A	data input
12	5Y	data output
13	NC	no connection
14	6A	data input
15	6Y	data output
16	NC	no connection

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4051 - 8-channel analog multiplexer/demultiplexer - msarnoff.org ChipDB

4051

8-channel analog multiplexer/demultiplexer


Y4	1 •	16	V_CC
Y6	2	15	Y2
Z	3	14	Y1
Y7	4	13	Y0
Y5	5	12	Y3
E	6	11	A0
V_EE	7	10	A1
GND	8	9	A2

Pin	Symbol	Description
1	Y4	independent input/output
2	Y6	independent input/output
3	Z	common input/output
4	Y7	independent input/output
5	Y5	independent input/output
6	E	enable input (active low)
7	V_EE	switch negative supply voltage
8	GND	ground
9	A2	address input
10	A1	address input
11	A0	address input
12	Y3	independent input/output
13	Y0	independent input/output
14	Y1	independent input/output
15	Y2	independent input/output
16	V_CC	supply voltage

Notes

The device contains eight bidirectional analog switches.

The analog inputs/outputs can swing between V_CC and V_EE.

When E is high, all switches are in a high-impedance off state.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4052 - Dual 4-channel analog multiplexer/demultiplexer - msarnoff.org ChipDB

4052

Dual 4-channel analog multiplexer/demultiplexer


Y_0B	1 •	16	V_CC
Y_2B	2	15	Y_2A
Z_B	3	14	Y_1A
Y_3B	4	13	Z_A
Y_1B	5	12	Y_0A
E	6	11	Y_3A
V_EE	7	10	A₀
GND	8	9	A₁

Pin	Symbol	Description
1	Y_0B	independent input/output
2	Y_2B	independent input/output
3	Z_B	common input/output
4	Y_3B	independent input/output
5	Y_1B	independent input/output
6	E	enable input (active low)
7	V_EE	switch negative supply voltage
8	GND	ground
9	A₁	address input
10	A₀	address input
11	Y_3A	independent input/output
12	Y_0A	independent input/output
13	Z_A	common input/output
14	Y_1A	independent input/output
15	Y_2A	independent input/output
16	V_CC	supply voltage

Notes

The device contains four bidirectional analog switches.

The analog inputs/outputs can swing between V_CC and V_EE.

When E is high, all switches are in a high-impedance off state.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4053 - Triple 2-channel analog multiplexer/demultiplexer (triple SPDT analog switch) - msarnoff.org ChipDB

4053

Triple 2-channel analog multiplexer/demultiplexer (triple SPDT analog switch)


Y_1B	1 •	16	V_CC
Y_0B	2	15	Z_B
Y_1C	3	14	Z_A
Z_C	4	13	Y_1A
Y_0C	5	12	Y_0A
E	6	11	S_A
V_EE	7	10	S_B
GND	8	9	S_C

Pin	Symbol	Description
1	Y_1B	independent input/output
2	Y_0B	independent input/output
3	Y_1C	independent input/output
4	Z_C	common input/output
5	Y_0C	independent input/output
6	E	enable input (active low)
7	V_EE	switch negative supply voltage
8	GND	ground
9	S_C	select input
10	S_B	select input
11	S_A	select input
12	Y_0A	independent input/output
13	Y_1A	independent input/output
14	Z_A	common input/output
15	Z_B	common input/output
16	V_CC	supply voltage

Notes

Each multiplexer/demultiplexer contains two bidirectional analog switches.

The analog inputs/outputs can swing between V_CC and V_EE.

When E is high, all switches are in a high-impedance off state.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4060 - 14-stage ripple-carry binary counter/divider and oscillator - msarnoff.org ChipDB

4060

14-stage ripple-carry binary counter/divider and oscillator


Q11	1 •	16	Vcc
Q12	2	15	Q₉
Q13	3	14	Q₇
Q5	4	13	Q₈
Q4	5	12	MR
Q6	6	11	RS
Q3	7	10	R_TC
GND	8	9	C_TC

Pin	Symbol	Description
1	Q11	counter output
2	Q12	counter output
3	Q13	counter output
4	Q5	counter output
5	Q4	counter output
6	Q6	counter output
7	Q3	counter output
8	GND	ground
9	C_TC	external capacitor connection
10	R_TC	oscillator pin
11	RS	clock input/oscillator pin (high-to-low edge-triggered)
12	MR	master reset (active high)
13	Q₈	counter output
14	Q₇	counter output
15	Q₉	counter output
16	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4066 - Quad bilateral switch - msarnoff.org ChipDB

4066

Quad bilateral switch


IN 1	1 •	14	V_DD
OUT 1	2	13	CONTROL 1
OUT 2	3	12	CONTROL 4
IN 2	4	11	IN 4
CONTROL 2	5	10	OUT 4
CONTROL 3	6	9	OUT 3
V_SS	7	8	IN 3

Pin	Symbol	Description
1	IN 1	switch 1 input
2	OUT 1	switch 1 output
3	OUT 2	switch 2 output
4	IN 2	switch 2 input
5	CONTROL 2	switch 2 control
6	CONTROL 3	switch 3 control
7	V_SS	ground/negative supply voltage
8	IN 3	switch 3 input
9	OUT 3	switch 3 output
10	OUT 4	switch 4 output
11	IN 4	switch 4 input
12	CONTROL 4	switch 4 control
13	CONTROL 1	switch 1 control
14	V_DD	positive supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum switching frequency	40	MHz
Maximum supply voltage	18	V
Maximum switch through current	± 25	mA

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4067 - 16-channel analog multiplexer/demultiplexer - msarnoff.org ChipDB

4067

16-channel analog multiplexer/demultiplexer


Z	1 •	24	V_CC
Y7	2	23	Y8
Y6	3	22	Y9
Y5	4	21	Y10
Y4	5	20	Y11
Y3	6	19	Y12
Y2	7	18	Y13
Y1	8	17	Y14
Y0	9	16	Y15
A0	10	15	E
A1	11	14	A2
GND	12	13	A3

Pin	Symbol	Description
1	Z	common input/output
2	Y7	independent input/output
3	Y6	independent input/output
4	Y5	independent input/output
5	Y4	independent input/output
6	Y3	independent input/output
7	Y2	independent input/output
8	Y1	independent input/output
9	Y0	independent input/output
10	A0	address input
11	A1	address input
12	GND	ground
13	A3	address input
14	A2	address input
15	E	enable input (active low)
16	Y15	independent input/output
17	Y14	independent input/output
18	Y13	independent input/output
19	Y12	independent input/output
20	Y11	independent input/output
21	Y10	independent input/output
22	Y9	independent input/output
23	Y8	independent input/output
24	V_CC	supply voltage

Notes

The device contains sixteen bidirectional analog switches.

The analog inputs/outputs can swing between V_CC and GND.

When E is high, all switches are in a high-impedance off state.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4068 - 8-input NAND gate - msarnoff.org ChipDB

4068

8-input NAND gate


NC	1 •	14	Vcc
I₀	2	13	Y
I₁	3	12	I₇
I₂	4	11	I₆
I₃	5	10	I₅
NC	6	9	I₄
GND	7	8	NC

Pin	Symbol	Description
1	NC	no connection
2	I₀	data input
3	I₁	data input
4	I₂	data input
5	I₃	data input
6	NC	no connection
7	GND	ground
8	NC	no connection
9	I₄	data input
10	I₅	data input
11	I₆	data input
12	I₇	data input
13	Y	data output
14	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4069 - Hex inverter - msarnoff.org ChipDB

4069

Hex inverter


1A	1 •	14	Vcc
1Y	2	13	6A
2A	3	12	6Y
2Y	4	11	5A
3A	5	10	5Y
3Y	6	9	4A
GND	7	8	4Y

Pin	Symbol	Description
1	1A	data input
2	1Y	data output
3	2A	data input
4	2Y	data output
5	3A	data input
6	3Y	data output
7	GND	ground
8	4Y	data output
9	4A	data input
10	5Y	data output
11	5A	data input
12	6Y	data output
13	6A	data input
14	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4070 - Quad 2-input XOR gate - msarnoff.org ChipDB

4070

Quad 2-input XOR gate


1A	1 •	14	Vcc
1B	2	13	4B
1Y	3	12	4A
2Y	4	11	4Y
2A	5	10	3Y
2B	6	9	3B
GND	7	8	3A

Pin	Symbol	Description
1	1A	data input
2	1B	data input
3	1Y	data output
4	2Y	data output
5	2A	data input
6	2B	data input
7	GND	ground
8	3A	data input
9	3B	data input
10	3Y	data output
11	4Y	data output
12	4A	data input
13	4B	data input
14	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4071 - Quad 2-input OR gate - msarnoff.org ChipDB

4071

Quad 2-input OR gate


1A	1 •	14	Vcc
1B	2	13	4B
1Y	3	12	4A
2Y	4	11	4Y
2A	5	10	3Y
2B	6	9	3B
GND	7	8	3A

Pin	Symbol	Description
1	1A	data input
2	1B	data input
3	1Y	data output
4	2Y	data output
5	2A	data input
6	2B	data input
7	GND	ground
8	3A	data input
9	3B	data input
10	3Y	data output
11	4Y	data output
12	4A	data input
13	4B	data input
14	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4072 - Dual 4-input OR gate - msarnoff.org ChipDB

4072

Dual 4-input OR gate


1Y	1 •	14	Vcc
1A	2	13	2Y
1B	3	12	2D
1C	4	11	2C
1D	5	10	2B
NC	6	9	2A
GND	7	8	NC

Pin	Symbol	Description
1	1Y	data output
2	1A	data input
3	1B	data input
4	1C	data input
5	1D	data input
6	NC	no connection
7	GND	ground
8	NC	no connection
9	2A	data input
10	2B	data input
11	2C	data input
12	2D	data input
13	2Y	data output
14	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4073 - Triple 3-input AND gate - msarnoff.org ChipDB

4073

Triple 3-input AND gate


2A	1 •	14	Vcc
2B	2	13	3C
1A	3	12	3B
1B	4	11	3A
1C	5	10	3Y
1Y	6	9	2Y
GND	7	8	2C

Pin	Symbol	Description
1	2A	data input
2	2B	data input
3	1A	data input
4	1B	data input
5	1C	data input
6	1Y	data output
7	GND	ground
8	2C	data input
9	2Y	data output
10	3Y	data output
11	3A	data input
12	3B	data input
13	3C	data input
14	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4075 - Triple 3-input OR gate - msarnoff.org ChipDB

4075

Triple 3-input OR gate


2A	1 •	14	Vcc
2B	2	13	3C
1A	3	12	3B
1B	4	11	3A
1C	5	10	3Y
1Y	6	9	2Y
GND	7	8	2C

Pin	Symbol	Description
1	2A	data input
2	2B	data input
3	1A	data input
4	1B	data input
5	1C	data input
6	1Y	data output
7	GND	ground
8	2C	data input
9	2Y	data output
10	3Y	data output
11	3A	data input
12	3B	data input
13	3C	data input
14	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4077 - Quad 2-input XNOR gate - msarnoff.org ChipDB

4077

Quad 2-input XNOR gate


1A	1 •	14	Vcc
1B	2	13	4B
1Y	3	12	4A
2Y	4	11	4Y
2A	5	10	3Y
2B	6	9	3B
GND	7	8	3A

Pin	Symbol	Description
1	1A	data input
2	1B	data input
3	1Y	data output
4	2Y	data output
5	2A	data input
6	2B	data input
7	GND	ground
8	3A	data input
9	3B	data input
10	3Y	data output
11	4Y	data output
12	4A	data input
13	4B	data input
14	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4081 - Quad 2-input AND gate - msarnoff.org ChipDB

4081

Quad 2-input AND gate


1A	1 •	14	Vcc
1B	2	13	4B
1Y	3	12	4A
2Y	4	11	4Y
2A	5	10	3Y
2B	6	9	3B
GND	7	8	3A

Pin	Symbol	Description
1	1A	data input
2	1B	data input
3	1Y	data output
4	2Y	data output
5	2A	data input
6	2B	data input
7	GND	ground
8	3A	data input
9	3B	data input
10	3Y	data output
11	4Y	data output
12	4A	data input
13	4B	data input
14	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4082 - Dual 4-input AND gate - msarnoff.org ChipDB

4082

Dual 4-input AND gate


1Y	1 •	14	Vcc
1A	2	13	2Y
1B	3	12	2D
1C	4	11	2C
1D	5	10	2B
NC	6	9	2A
GND	7	8	NC

Pin	Symbol	Description
1	1Y	data output
2	1A	data input
3	1B	data input
4	1C	data input
5	1D	data input
6	NC	no connection
7	GND	ground
8	NC	no connection
9	2A	data input
10	2B	data input
11	2C	data input
12	2D	data input
13	2Y	data output
14	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4085 - Dual 2-wide 2-input AND-OR-INVERT gate - msarnoff.org ChipDB

4085

Dual 2-wide 2-input AND-OR-INVERT gate


A1	1 •	14	Vcc
B1	2	13	D1
Q1	3	12	C1
Q2	4	11	INH2
A2	5	10	INH1
B2	6	9	D2
GND	7	8	C2

Pin	Symbol	Description
1	A1	data input
2	B1	data input
3	Q1	data output (see note)
4	Q2	data output (see note)
5	A2	data input
6	B2	data input
7	GND	ground
8	C2	data input
9	D2	data input
10	INH1	inhibit
11	INH2	inhibit
12	C1	data input
13	D1	data input
14	Vcc	supply voltage

Notes

Q = INH OR (A AND B) OR (C AND D)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4093 - Quad 2-input NAND Schmitt trigger - msarnoff.org ChipDB

4093

Quad 2-input NAND Schmitt trigger


1A	1 •	14	Vcc
1B	2	13	4B
1Y	3	12	4A
2Y	4	11	4Y
2A	5	10	3Y
2B	6	9	3B
GND	7	8	3A

Pin	Symbol	Description
1	1A	data input
2	1B	data input
3	1Y	data output
4	2Y	data output
5	2A	data input
6	2B	data input
7	GND	ground
8	3A	data input
9	3B	data input
10	3Y	data output
11	4Y	data output
12	4A	data input
13	4B	data input
14	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4094 - 8-stage shift-and-store bus register - msarnoff.org ChipDB

4094

8-stage shift-and-store bus register


STR	1 •	16	Vcc
D	2	15	OE
CP	3	14	QP4
QP0	4	13	QP5
QP1	5	12	QP6
QP2	6	11	QP7
QP3	7	10	QS2
GND	8	9	QS1

Pin	Symbol	Description
1	STR	strobe input (active high)
2	D	data input
3	CP	clock input (low-to-high edge-triggered)
4	QP0	parallel output
5	QP1	parallel output
6	QP2	parallel output
7	QP3	parallel output
8	GND	ground
9	QS1	serial output
10	QS2	serial output
11	QP7	parallel output
12	QP6	parallel output
13	QP5	parallel output
14	QP4	parallel output
15	OE	output enable
16	Vcc	supply voltage (active high)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4099 - 8-bit addressable latch - msarnoff.org ChipDB

4099

8-bit addressable latch


Q7	1 •	16	Vcc
RESET	2	15	Q6
DATA	3	14	Q5
WRITE	4	13	Q4
A0	5	12	Q3
A1	6	11	Q2
A2	7	10	Q1
GND	8	9	Q0

Pin	Symbol	Description
1	Q7	latch output
2	RESET	master reset (all bits to 0; active high)
3	DATA	data input
4	WRITE	write enable (active low)
5	A0	address input
6	A1	address input
7	A2	address input
8	GND	ground
9	Q0	latch output
10	Q1	latch output
11	Q2	latch output
12	Q3	latch output
13	Q4	latch output
14	Q5	latch output
15	Q6	latch output
16	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4511 - BCD to 7-segment latch/decoder/driver - msarnoff.org ChipDB

4511

BCD to 7-segment latch/decoder/driver


D1	1 •	16	Vcc
D2	2	15	Qg
LT	3	14	Qf
BL	4	13	Qa
LE	5	12	Qb
D3	6	11	Qc
D0	7	10	Qd
GND	8	9	Qe

Pin	Symbol	Description
1	D1	BCD input
2	D2	BCD input
3	LT	lamp test (lights all segments, active low)
4	BL	blank (active low)
5	LE	latch enable (active high)
6	D3	BCD input
7	D0	BCD input
8	GND	ground
9	Qe	segment output
10	Qd	segment output
11	Qc	segment output
12	Qb	segment output
13	Qa	segment output
14	Qf	segment output
15	Qg	segment output
16	Vcc	supply voltage

Notes

Pins for lit segments are high. The 4511 can directly drive a common cathode LED display.

Display is blanked for inputs greater than 9.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4514 - 1-of-16 decoder/demultiplexer with input latches - msarnoff.org ChipDB

4514

1-of-16 decoder/demultiplexer with input latches


LE	1 •	24	Vcc
A0	2	23	E
A1	3	22	A3
Q7	4	21	A2
Q6	5	20	Q10
Q5	6	19	Q11
Q4	7	18	Q8
Q3	8	17	Q9
Q1	9	16	Q14
Q2	10	15	Q15
Q0	11	14	Q12
GND	12	13	Q13

Pin	Symbol	Description
1	LE	latch enable (active high)
2	A0	address input
3	A1	address input
4	Q7	output
5	Q6	output
6	Q5	output
7	Q4	output
8	Q3	output
9	Q1	output
10	Q2	output
11	Q0	output
12	GND	ground
13	Q13	output
14	Q12	output
15	Q15	output
16	Q14	output
17	Q9	output
18	Q8	output
19	Q11	output
20	Q10	output
21	A2	address input
22	A3	address input
23	E	enable (active low)
24	Vcc	supply voltage

Notes

Outputs are mutually exclusive active high.

When E is high, all outputs are low.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4515 - 1-of-16 decoder/demultiplexer with input latches; inverting - msarnoff.org ChipDB

4515

1-of-16 decoder/demultiplexer with input latches; inverting


LE	1 •	24	Vcc
A0	2	23	E
A1	3	22	A3
Q7	4	21	A2
Q6	5	20	Q10
Q5	6	19	Q11
Q4	7	18	Q8
Q3	8	17	Q9
Q1	9	16	Q14
Q2	10	15	Q15
Q0	11	14	Q12
GND	12	13	Q13

Pin	Symbol	Description
1	LE	latch enable (active high)
2	A0	address input
3	A1	address input
4	Q7	output
5	Q6	output
6	Q5	output
7	Q4	output
8	Q3	output
9	Q1	output
10	Q2	output
11	Q0	output
12	GND	ground
13	Q13	output
14	Q12	output
15	Q15	output
16	Q14	output
17	Q9	output
18	Q8	output
19	Q11	output
20	Q10	output
21	A2	address input
22	A3	address input
23	E	enable (active low)
24	Vcc	supply voltage

Notes

Outputs are mutually exclusive active low.

When E is high, all outputs are high.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4516 - 4-bit binary up/down counter - msarnoff.org ChipDB

4516

4-bit binary up/down counter


PL	1 •	16	Vcc
Q3	2	15	CP
D3	3	14	Q2
D0	4	13	D2
CE	5	12	D1
Q0	6	11	Q1
TC	7	10	UP/DN
GND	8	9	MR

Pin	Symbol	Description
1	PL	parallel load (active high)
2	Q3	count output
3	D3	parallel input
4	D0	parallel input
5	CE	count enable (active low)
6	Q0	count output
7	TC	terminal count output (active low)
8	GND	ground
9	MR	master reset (active high)
10	UP/DN	up/down count control
11	Q1	count output
12	D1	parallel input
13	D2	parallel input
14	Q2	count output
15	CP	clock input (low-to-high edge-triggered)
16	Vcc	supply voltage

Notes

When counting up, TC goes low when the count is 15.

When counting down, TC goes low when the count is 0.

TC is always high when CE is high (counting is disabled).

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4518 - Dual synchronous BCD counter - msarnoff.org ChipDB

4518

Dual synchronous BCD counter


1CP0	1 •	16	Vcc
1CP1	2	15	2MR
1Q0	3	14	2Q3
1Q1	4	13	2Q2
1Q2	5	12	2Q1
1Q3	6	11	2Q0
1MR	7	10	2CP1
GND	8	9	2CP0

Pin	Symbol	Description
1	1CP0	counter 1 clock input (low-to-high triggered)
2	1CP1	counter 1 clock input (high-to-low triggered)
3	1Q0	counter 1 output
4	1Q1	counter 1 output
5	1Q2	counter 1 output
6	1Q3	counter 1 output
7	1MR	counter 1 master reset (active high)
8	GND	ground
9	2CP0	counter 2 clock input (low-to-high triggered)
10	2CP1	counter 2 clock input (high-to-low triggered)
11	2Q0	counter 2 output
12	2Q1	counter 2 output
13	2Q2	counter 2 output
14	2Q3	counter 2 output
15	2MR	counter 2 master reset (active high)
16	Vcc	supply voltage

Notes

The 4518 counts from 0 to 9. The 4520 is identical but counts from 0 to 15.

Either nCP0 or nCP1 may be used as the clock input; the other can be used as a clock enable input.

If nCP1 is high, the counter advances on a low-to-high transition of nCP0.

If nCP0 is low, the counter advances on a high-to-low transition of nCP1.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4520 - Dual 4-bit synchronous binary counter - msarnoff.org ChipDB

4520

Dual 4-bit synchronous binary counter


1CP0	1 •	16	Vcc
1CP1	2	15	2MR
1Q0	3	14	2Q3
1Q1	4	13	2Q2
1Q2	5	12	2Q1
1Q3	6	11	2Q0
1MR	7	10	2CP1
GND	8	9	2CP0

Pin	Symbol	Description
1	1CP0	counter 1 clock input (low-to-high triggered)
2	1CP1	counter 1 clock input (high-to-low triggered)
3	1Q0	counter 1 output
4	1Q1	counter 1 output
5	1Q2	counter 1 output
6	1Q3	counter 1 output
7	1MR	counter 1 master reset (active high)
8	GND	ground
9	2CP0	counter 2 clock input (low-to-high triggered)
10	2CP1	counter 2 clock input (high-to-low triggered)
11	2Q0	counter 2 output
12	2Q1	counter 2 output
13	2Q2	counter 2 output
14	2Q3	counter 2 output
15	2MR	counter 2 master reset (active high)
16	Vcc	supply voltage

Notes

The 4520 counts from 0 to 15. The 4518 is identical but counts from 0 to 9.

Either nCP0 or nCP1 may be used as the clock input; the other can be used as a clock enable input.

If nCP1 is high, the counter advances on a low-to-high transition of nCP0.

If nCP0 is low, the counter advances on a high-to-low transition of nCP1.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4526 - Programmable 4-bit binary down counter - msarnoff.org ChipDB

4526

Programmable 4-bit binary down counter


Q3	1 •	16	Vcc
P3	2	15	Q2
PL	3	14	P2
CP1	4	13	CF
P0	5	12	TC
CP0	6	11	P1
Q0	7	10	MR
GND	8	9	Q1

Pin	Symbol	Description
1	Q3	count output
2	P3	parallel input
3	PL	parallel load (active high)
4	CP1	clock input (high-to-low triggered)
5	P0	parallel input
6	CP0	clock input (low-to-high triggered)
7	Q0	count output
8	GND	ground
9	Q1	count output
10	MR	asynchronous master reset (active high)
11	P1	parallel input
12	TC	terminal count output
13	CF	cascade feedback input
14	P2	parallel input
15	Q2	count output
16	Vcc	supply voltage

Notes

When CP1 is low, the counter advances on a low-to-high transition of CP0.

When CP0 is high, the counter advances on a high-to-low transition of CP1.

TC goes high when the count is 0, CF is high, and PL is low.

For a single-stage divide-by-n circuit, connect the TC output to PL and set the P0-P3 inputs to n.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4528 - Dual retriggerable monostable multivibrator with reset - msarnoff.org ChipDB

4528

Dual retriggerable monostable multivibrator with reset


1CEXT	1 •	16	Vcc
1REXT/CEXT	2	15	2CEXT
1CD	3	14	2REXT/CEXT
1B	4	13	2CD
1A	5	12	2B
1Q	6	11	2A
1Q	7	10	2Q
GND	8	9	2Q

Pin	Symbol	Description
1	1CEXT	external capacitor connection (connect to capacitor and ground)
2	1REXT/CEXT	external capacitor/resistor connection
3	1CD	clear direct input (active low)
4	1B	input (low-to-high triggered)
5	1A	input (high-to-low triggered)
6	1Q	output
7	1Q	complementary output
8	GND	ground
9	2Q	complementary output
10	2Q	output
11	2A	input (high-to-low triggered)
12	2B	input (low-to-high triggered)
13	2CD	clear direct input (active low)
14	2REXT/CEXT	external capacitor/resistor connection
15	2CEXT	external capacitor connection (connect to capacitor and ground)
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
External timing resistor R_EXT	5 (min) 2000 (max)	kΩ
Pulse width variation, Vcc = 5V	±3	%

Notes

Connect a timing capacitor C_EXT between nCEXT and nREXT/CEXT.

Connect a resistor R_EXT between nREXT/CEXT and Vcc.

A high-to-low transition on nA when nB is low causes a pulse on nQ and nQ.

A low-to-high transition on nB when nA is high causes a pulse on nQ and nQ.

Setting nCD low inhibits pulses.

(CD4528) For C_EXT > 0.01 µF and Vcc = 5V, output pulse width = 0.2 × R_EXT × C_EXT.

(HEF4528) For C_EXT > 0.01 µF and Vcc = 5V, output pulse width = 0.42 × R_EXT × C_EXT.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4538 - Dual retriggerable precision monostable multivibrator with reset - msarnoff.org ChipDB

4538

Dual retriggerable precision monostable multivibrator with reset


1CEXT	1 •	16	Vcc
1REXT/CEXT	2	15	2CEXT
1CD	3	14	2REXT/CEXT
1B	4	13	2CD
1A	5	12	2B
1Q	6	11	2A
1Q	7	10	2Q
GND	8	9	2Q

Pin	Symbol	Description
1	1CEXT	external capacitor connection (connect to capacitor and ground)
2	1REXT/CEXT	external capacitor/resistor connection
3	1CD	clear direct input (active low)
4	1B	input (low-to-high triggered)
5	1A	input (high-to-low triggered)
6	1Q	output
7	1Q	complementary output
8	GND	ground
9	2Q	complementary output
10	2Q	output
11	2A	input (high-to-low triggered)
12	2B	input (low-to-high triggered)
13	2CD	clear direct input (active low)
14	2REXT/CEXT	external capacitor/resistor connection
15	2CEXT	external capacitor connection (connect to capacitor and ground)
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
External timing resistor R_EXT	5 (min)	kΩ
External timing capacitor C_EXT	2000 (min)	pF
Pulse width variation, Vcc = 5V	±0.2	%

Notes

Connect a timing capacitor C_EXT between nCEXT and nREXT/CEXT.

Connect a resistor R_EXT between nREXT/CEXT and Vcc.

A high-to-low transition on nA when nB is low causes a pulse on nQ and nQ.

A low-to-high transition on nB when nA is high causes a pulse on nQ and nQ.

Setting nCD low inhibits pulses.

Output pulse width = R_EXT × C_EXT.

(74HC4538) Output pulse width = 0.7 × R_EXT × C_EXT.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4541 - Programmable timer - msarnoff.org ChipDB

4541

Programmable timer


R_TC	1 •	14	Vcc
C_TC	2	13	A1
RS	3	12	A0
NC	4	11	NC
AR	5	10	MODE
MR	6	9	PH
GND	7	8	O

Pin	Symbol	Description
1	R_TC	external resistor connection (R_t)
2	C_TC	external capacitor connection (C_t)
3	RS	external resistor connection (R_S) or external clock input
4	NC	no connection
5	AR	auto reset input (active low)
6	MR	master reset input (active high)
7	GND	ground
8	O	output
9	PH	phase input
10	MODE	mode select (single cycle or continuous)
11	NC	no connection
12	A0	divider input
13	A1	divider input
14	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Frequency range	1 (min) 100k (max)	Hz
External capacitor C_t	100 (min)	pF
External resistor R_t	10k (min) 1M (max)	Ω

Notes

The RC oscillator frequency is 1/(2.3 × R_t × C_t). R_S = 2R_t.

An external clock signal, connected to RS, may be used instead. The timer advances on the low-to-high transition of RS.

The input frequency is divided by a value determined by A1A0: 2¹³ (LL), 2¹⁰ (LH), 2⁸ (HL), or 2¹⁶ (HH).

Power-on reset is enabled when AR and MR are low. For HEF4541, Vcc should be above 8.5V for correct power-on reset.

PH specifies the state of the output after reset (high or low).

When MODE is high, the output oscillates continuously.

When MODE is low, the output changes only once, after a single cycle.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4555 - Dual 1-of-4 decoder/demultiplexer - msarnoff.org ChipDB

4555

Dual 1-of-4 decoder/demultiplexer


1E	1 •	16	Vcc
1A₀	2	15	2E
1A₁	3	14	2A₀
1Y₀	4	13	2A₁
1Y₁	5	12	2Y₀
1Y₂	6	11	2Y₁
1Y₃	7	10	2Y₂
GND	8	9	2Y₃

Pin	Symbol	Description
1	1E	enable input (active low)
2	1A₀	address input
3	1A₁	address input
4	1Y₀	output
5	1Y₁	output
6	1Y₂	output
7	1Y₃	output
8	GND	ground
9	2Y₃	output
10	2Y₂	output
11	2Y₁	output
12	2Y₀	output
13	2A₁	address input
14	2A₀	address input
15	2E	enable input (active low)
16	Vcc	supply voltage

Notes

Outputs are mutually exclusive, active high.

When nE is high, all outputs nY are low.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4556 - Dual 1-of-4 decoder/demultiplexer; inverting - msarnoff.org ChipDB

4556

Dual 1-of-4 decoder/demultiplexer; inverting


1E	1 •	16	Vcc
1A₀	2	15	2E
1A₁	3	14	2A₀
1Y₀	4	13	2A₁
1Y₁	5	12	2Y₀
1Y₂	6	11	2Y₁
1Y₃	7	10	2Y₂
GND	8	9	2Y₃

Pin	Symbol	Description
1	1E	enable input (active low)
2	1A₀	address input
3	1A₁	address input
4	1Y₀	output
5	1Y₁	output
6	1Y₂	output
7	1Y₃	output
8	GND	ground
9	2Y₃	output
10	2Y₂	output
11	2Y₁	output
12	2Y₀	output
13	2A₁	address input
14	2A₀	address input
15	2E	enable input (active low)
16	Vcc	supply voltage

Notes

Outputs are mutually exclusive, active low.

When nE is high, all outputs nY are high.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4557 - 1-to-64 bit variable length shift register - msarnoff.org ChipDB

4557

1-to-64 bit variable length shift register


L₂	1 •	16	Vcc
L₁	2	15	L₄
MR	3	14	L₈
CP₀	4	13	L₁₆
CP₁	5	12	L₃₂
D_B	6	11	Q
D_A	7	10	Q
GND	8	9	A/B

Pin	Symbol	Description
1	L₂	length control input
2	L₁	length control input
3	MR	asynchronous master reset
4	CP₀	clock input (low-to-high edge-triggered)
5	CP₁	clock input (high-to-low edge-triggered)
6	D_B	data input
7	D_A	data input
8	GND	ground
9	A/B	select data input
10	Q	output
11	Q	complementary output
12	L₃₂	length input
13	L₁₆	length input
14	L₈	length input
15	L₄	length input
16	Vcc	supply voltage

Notes

The length of the shift register is determined by the sum of the length inputs (L₁, L₂, L₄, L₈, L₁₆, L₃₂) plus one.

Data is shifted in on the low-to-high transition of CP₀ when CP₁ is low, or the high-to-low transition of CP₁ when CP₀ is high.

When A/B is high, a clock pulse shifts in data from D_A. When low, a clock pulse shifts in data from D_B.

When MR is high, the register is reset, Q is forced low, and Q is forced high.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4572 - Hex gate (four inverters, one 2-input NOR gate, one 2-input NAND gate) - msarnoff.org ChipDB

4572

Hex gate (four inverters, one 2-input NOR gate, one 2-input NAND gate)


A	1 •	16	Vcc
A	2	15	H
B	3	14	G
B	4	13	G NAND H
C NOR D	5	12	F
C	6	11	F
D	7	10	E
GND	8	9	E

Pin	Symbol	Description
1	A	inverter 1 output
2	A	inverter 1 input
3	B	inverter 2 output
4	B	inverter 2 input
5	C NOR D	NOR gate output
6	C	NOR gate input
7	D	NOR gate input
8	GND	ground
9	E	inverter 3 output
10	E	inverter 3 input
11	F	inverter 4 output
12	F	inverter 4 input
13	G NAND H	NAND gate output
14	G	NAND gate input
15	H	NAND gate input
16	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4585 - 4-bit magnitude comparator - msarnoff.org ChipDB

4585

4-bit magnitude comparator


B₂	1 •	16	Vcc
A₂	2	15	A₃
Q_A=B	3	14	B₃
I_A>B	4	13	Q_A>B
I_A<B	5	12	Q_A<B
I_A=B	6	11	B₀
A₁	7	10	A₀
GND	8	9	B₁

Pin	Symbol	Description
1	B₂	word B input
2	A₂	word A input
3	Q_A=B	A = B output
4	I_A>B	A > B expansion input
5	I_A<B	A < B expansion input
6	I_A=B	A = B expansion input
7	A₁	word A input
8	GND	ground
9	B₁	word B input
10	A₀	word A input
11	B₀	word B input
12	Q_A<B	A < B output
13	Q_A>B	A > B output
14	B₃	word B input
15	A₃	word A input
16	Vcc	supply voltage

Notes

The least significant (or only) comparator in a chain should have I_A=B and I_A>B tied high and I_A<B tied low.

To compare more than 4 bits, connect Q_A<B and Q_A=B to the inputs of the next significant comparator. I_A>B of the next significant comparator should be tied high.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4N35M - Phototransistor output optocoupler - msarnoff.org ChipDB

4N35M

Phototransistor output optocoupler


A	1 •	6	B
K	2	5	C
NC	3	4	E

Pin	Symbol	Description
1	A	anode
2	K	cathode
3	NC	no connection
4	E	emitter
5	C	collector
6	B	base

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Input forward voltage, typical	1.18	V
Input forward voltage, maximum	1.5	V
Input current, maximum	60	ma
Current transfer ratio, collector to emitter	100 (4N35M/4N36M/4N37M) 50 (H11A1M) 30 (H11A5M) 20 (4N25M/4N26M/H11A2M/H11A3M) 10 (4N27M/4N28M/H11A4M)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

40106 - Hex inverting Schmitt trigger - msarnoff.org ChipDB

40106

Hex inverting Schmitt trigger


1A	1 •	14	Vcc
1Y	2	13	6A
2A	3	12	6Y
2Y	4	11	5A
3A	5	10	5Y
3Y	6	9	4A
GND	7	8	4Y

Pin	Symbol	Description
1	1A	data input
2	1Y	data output
3	2A	data input
4	2Y	data output
5	3A	data input
6	3Y	data output
7	GND	ground
8	4Y	data output
9	4A	data input
10	5Y	data output
11	5A	data input
12	6Y	data output
13	6A	data input
14	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

40193 - 4-bit up/down binary counter - msarnoff.org ChipDB

40193

4-bit up/down binary counter


D1	1 •	16	Vcc
Q1	2	15	D0
Q0	3	14	MR
CPD	4	13	TCD
CPU	5	12	TCU
Q2	6	11	PL
Q3	7	10	D2
GND	8	9	D3

Pin	Symbol	Description
1	D1	parallel data input
2	Q1	count output
3	Q0	count output
4	CPD	count-down clock input (low-to-high edge-triggered)
5	CPU	count-up clock input (low-to-high edge-triggered)
6	Q2	count output
7	Q3	count output
8	GND	ground
9	D3	parallel data input
10	D2	parallel data input
11	PL	parallel load (active low)
12	TCU	terminal count-up (carry; active low)
13	TCD	terminal count-down (borrow; active low)
14	MR	master reset
15	D0	parallel data input
16	Vcc	supply voltage

Notes

TCU goes low when the count is 15.

TCD goes low when the count is 0.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4N35M - Phototransistor output optocoupler - msarnoff.org ChipDB

4N35M

Phototransistor output optocoupler


A	1 •	6	B
K	2	5	C
NC	3	4	E

Pin	Symbol	Description
1	A	anode
2	K	cathode
3	NC	no connection
4	E	emitter
5	C	collector
6	B	base

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Input forward voltage, typical	1.18	V
Input forward voltage, maximum	1.5	V
Input current, maximum	60	ma
Current transfer ratio, collector to emitter	100 (4N35M/4N36M/4N37M) 50 (H11A1M) 30 (H11A5M) 20 (4N25M/4N26M/H11A2M/H11A3M) 10 (4N27M/4N28M/H11A4M)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4N35M - Phototransistor output optocoupler - msarnoff.org ChipDB

4N35M

Phototransistor output optocoupler


A	1 •	6	B
K	2	5	C
NC	3	4	E

Pin	Symbol	Description
1	A	anode
2	K	cathode
3	NC	no connection
4	E	emitter
5	C	collector
6	B	base

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Input forward voltage, typical	1.18	V
Input forward voltage, maximum	1.5	V
Input current, maximum	60	ma
Current transfer ratio, collector to emitter	100 (4N35M/4N36M/4N37M) 50 (H11A1M) 30 (H11A5M) 20 (4N25M/4N26M/H11A2M/H11A3M) 10 (4N27M/4N28M/H11A4M)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4N35M - Phototransistor output optocoupler - msarnoff.org ChipDB

4N35M

Phototransistor output optocoupler


A	1 •	6	B
K	2	5	C
NC	3	4	E

Pin	Symbol	Description
1	A	anode
2	K	cathode
3	NC	no connection
4	E	emitter
5	C	collector
6	B	base

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Input forward voltage, typical	1.18	V
Input forward voltage, maximum	1.5	V
Input current, maximum	60	ma
Current transfer ratio, collector to emitter	100 (4N35M/4N36M/4N37M) 50 (H11A1M) 30 (H11A5M) 20 (4N25M/4N26M/H11A2M/H11A3M) 10 (4N27M/4N28M/H11A4M)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4N35M - Phototransistor output optocoupler - msarnoff.org ChipDB

4N35M

Phototransistor output optocoupler


A	1 •	6	B
K	2	5	C
NC	3	4	E

Pin	Symbol	Description
1	A	anode
2	K	cathode
3	NC	no connection
4	E	emitter
5	C	collector
6	B	base

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Input forward voltage, typical	1.18	V
Input forward voltage, maximum	1.5	V
Input current, maximum	60	ma
Current transfer ratio, collector to emitter	100 (4N35M/4N36M/4N37M) 50 (H11A1M) 30 (H11A5M) 20 (4N25M/4N26M/H11A2M/H11A3M) 10 (4N27M/4N28M/H11A4M)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4N35M - Phototransistor output optocoupler - msarnoff.org ChipDB

4N35M

Phototransistor output optocoupler


A	1 •	6	B
K	2	5	C
NC	3	4	E

Pin	Symbol	Description
1	A	anode
2	K	cathode
3	NC	no connection
4	E	emitter
5	C	collector
6	B	base

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Input forward voltage, typical	1.18	V
Input forward voltage, maximum	1.5	V
Input current, maximum	60	ma
Current transfer ratio, collector to emitter	100 (4N35M/4N36M/4N37M) 50 (H11A1M) 30 (H11A5M) 20 (4N25M/4N26M/H11A2M/H11A3M) 10 (4N27M/4N28M/H11A4M)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4N35M - Phototransistor output optocoupler - msarnoff.org ChipDB

4N35M

Phototransistor output optocoupler


A	1 •	6	B
K	2	5	C
NC	3	4	E

Pin	Symbol	Description
1	A	anode
2	K	cathode
3	NC	no connection
4	E	emitter
5	C	collector
6	B	base

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Input forward voltage, typical	1.18	V
Input forward voltage, maximum	1.5	V
Input current, maximum	60	ma
Current transfer ratio, collector to emitter	100 (4N35M/4N36M/4N37M) 50 (H11A1M) 30 (H11A5M) 20 (4N25M/4N26M/H11A2M/H11A3M) 10 (4N27M/4N28M/H11A4M)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

54374 - Octal D-type edge-triggered flip-flops with 3-state outputs - msarnoff.org ChipDB

54374

Octal D-type edge-triggered flip-flops with 3-state outputs


OE	1 •	20	Vcc
1Q	2	19	8Q
1D	3	18	D8D7
2D	4	17	7D
2Q	5	16	7Q
3Q	6	15	6Q
3D	7	14	6D
4D	8	13	5D
4Q	9	12	5Q
GND	10	11	CLK

Pin	Symbol	Description
1	OE	output enable (active low)
2	1Q	flip-flop output
3	1D	data input
4	2D	data input
5	2Q	flip-flop output
6	3Q	flip-flop output
7	3D	data input
8	4D	data input
9	4Q	flip-flop output
10	GND	ground
11	CLK	clock input (low-to-high, edge-triggered)
12	5Q	flip-flop output
13	5D	data input
14	6D	data input
15	6Q	flip-flop output
16	7Q	flip-flop output
17	7D	data input
18	D8D7	data input
19	8Q	flip-flop output
20	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Supply Voltage range	-0.5 to 7	V
Input Voltage range	-0.5 to 7	V
Recommended Voltage range	4.5 to 5.5	V
High level input voltage	2	V
Low-level input voltage	0.7 (54AL) 0.8 (74AL)	V
High-level output current	-1 (54AL) -2.6 (74AL)	mA
Low-level output current	12 (54AL) 24 (74AL)	mA
Operating Temp	-55 to +125 (54AL) 0 to +70 (74AL)	degC

Notes

OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state

released april 1982, revised november 1999

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

555 - Timer - msarnoff.org ChipDB
555
Timer

GND 1 • 8 Vcc
TRIG 2 7 DIS
OUT 3 6 THR
RESET 4 5 CV

Pin Symbol Description
1 GND ground
2 TRIG trigger
3 OUT output
4 RESET reset (active low)
5 CV control voltage
6 THR threshold
7 DIS discharge
8 Vcc supply voltage
Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Maximum supply voltage 18 V
Maximum output current (NE555) 200 mA
Power dissipation 600 mW

Notes
In monostable mode, pulse width ≈ 1.1RCIn astable mode, frequency = 1/(0.693*C*(R1+2*R2))In astable mode, pulse high time = 0.693*(R1+R2)*CIn astable mode, pulse low time = 0.693*R2*C
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

556 - Dual timer - msarnoff.org ChipDB

556

Dual timer


DIS 1	1 •	14	Vcc
THR 1	2	13	DIS 2
CV 1	3	12	THR 2
RESET 1	4	11	CV 2
OUT 1	5	10	RESET 2
TRIG 1	6	9	OUT 2
GND	7	8	TRIG 2

Pin	Symbol	Description
1	DIS 1	discharge (timer 1)
2	THR 1	threshold (timer 1)
3	CV 1	control voltage (timer 1)
4	RESET 1	reset (active low, timer 1)
5	OUT 1	output (timer 1)
6	TRIG 1	trigger (timer 1)
7	GND	ground
8	TRIG 2	trigger (timer 2)
9	OUT 2	output (timer 2)
10	RESET 2	reset (active low, timer 2)
11	CV 2	control voltage (timer 2)
12	THR 2	threshold (timer 2)
13	DIS 2	discharge (timer 2)
14	Vcc	supply voltage

Notes

The 556 contains two 555 timers.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

62256 - 32K x 8 static RAM - msarnoff.org ChipDB

62256

32K x 8 static RAM


A₁₄	1 •	28	Vcc
A₁₂	2	27	WE
A₇	3	26	A₁₃
A₆	4	25	A₈
A₅	5	24	A₉
A₄	6	23	A₁₁
A₃	7	22	OE
A₂	8	21	A₁₀
A₁	9	20	CE
A₀	10	19	I/O₇
I/O₀	11	18	I/O₆
I/O₁	12	17	I/O₅
I/O₂	13	16	I/O₄
GND	14	15	I/O₃

Pin	Symbol	Description
1	A₁₄	address input
2	A₁₂	address input
3	A₇	address input
4	A₆	address input
5	A₅	address input
6	A₄	address input
7	A₃	address input
8	A₂	address input
9	A₁	address input
10	A₀	address input
11	I/O₀	data input/output
12	I/O₁	data input/output
13	I/O₂	data input/output
14	GND	ground
15	I/O₃	data input/output
16	I/O₄	data input/output
17	I/O₅	data input/output
18	I/O₆	data input/output
19	I/O₇	data input/output
20	CE	chip enable (active low)
21	A₁₀	address input
22	OE	output enable (active low)
23	A₁₁	address input
24	A₉	address input
25	A₈	address input
26	A₁₃	address input
27	WE	write enable (active low)
28	Vcc	supply voltage

Notes

Data is written when CE is low and WE is low.

Data is read when CE is low, OE is low, and WE is high.

The input/output pins assume a high-impedance state if CE is high.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

6264 - 8K x 8 static RAM - msarnoff.org ChipDB

6264

8K x 8 static RAM


NC	1 •	28	Vcc
A₄	2	27	WE
A₅	3	26	CE₂
A₆	4	25	A₃
A₇	5	24	A₂
A₈	6	23	A₁
A₉	7	22	OE
A₁₀	8	21	A₀
A₁₁	9	20	CE₁
A₁₂	10	19	I/O₇
I/O₀	11	18	I/O₆
I/O₁	12	17	I/O₅
I/O₂	13	16	I/O₄
GND	14	15	I/O₃

Pin	Symbol	Description
1	NC	no connection
2	A₄	address input
3	A₅	address input
4	A₆	address input
5	A₇	address input
6	A₈	address input
7	A₉	address input
8	A₁₀	address input
9	A₁₁	address input
10	A₁₂	address input
11	I/O₀	data input/output
12	I/O₁	data input/output
13	I/O₂	data input/output
14	GND	ground
15	I/O₃	data input/output
16	I/O₄	data input/output
17	I/O₅	data input/output
18	I/O₆	data input/output
19	I/O₇	data input/output
20	CE₁	chip enable (active low)
21	A₀	address input
22	OE	output enable (active low)
23	A₁	address input
24	A₂	address input
25	A₃	address input
26	CE₂	chip enable (active high)
27	WE	write enable (active low)
28	Vcc	supply voltage

Notes

Data is written when CE₁ is low, WE is low, and CE₂ is high.

Data is read whem CE₁ is low, OE is low, and CE₂ is high.

The input/output pins assume a high-impedance state if the chip is not selected and/or OE is low.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

628128 - 128K x 8 static RAM - msarnoff.org ChipDB

628128

128K x 8 static RAM


NC	1 •	32	Vcc
A₁₆	2	31	A₁₅
A₁₄	3	30	CS2
A₁₂	4	29	WE
A₇	5	28	A₁₃
A₆	6	27	A₈
A₅	7	26	A₉
A₄	8	25	A₁₁
A₃	9	24	OE
A₂	10	23	A₁₀
A₁	11	22	CS1
A₀	12	21	I/O₇
I/O₀	13	20	I/O₆
I/O₁	14	19	I/O₅
I/O₂	15	18	I/O₄
GND	16	17	I/O₃

Pin	Symbol	Description
1	NC	no connection
2	A₁₆	address input
3	A₁₄	address input
4	A₁₂	address input
5	A₇	address input
6	A₆	address input
7	A₅	address input
8	A₄	address input
9	A₃	address input
10	A₂	address input
11	A₁	address input
12	A₀	address input
13	I/O₀	data input/output
14	I/O₁	data input/output
15	I/O₂	data input/output
16	GND	ground
17	I/O₃	data input/output
18	I/O₄	data input/output
19	I/O₅	data input/output
20	I/O₆	data input/output
21	I/O₇	data input/output
22	CS1	chip select (active low)
23	A₁₀	address input
24	OE	output enable (active low)
25	A₁₁	address input
26	A₉	address input
27	A₈	address input
28	A₁₃	address input
29	WE	write enable (active low)
30	CS2	chip select (active high)
31	A₁₅	address input
32	Vcc	supply voltage

Notes

Data is written when CS1 is low, CS2 is high, and WE is low.

Data is read when CS1 is low, CS2 is high, OE is low, and WE is high.

The input/output pins assume a high-impedance state if CS1 is high or CS2 is low.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

628512 - 512K x 8 static RAM - msarnoff.org ChipDB

628512

512K x 8 static RAM


A₁₈	1 •	32	Vcc
A₁₆	2	31	A₁₅
A₁₄	3	30	A₁₇
A₁₂	4	29	WE
A₇	5	28	A₁₃
A₆	6	27	A₈
A₅	7	26	A₉
A₄	8	25	A₁₁
A₃	9	24	OE
A₂	10	23	A₁₀
A₁	11	22	CS
A₀	12	21	I/O₇
I/O₀	13	20	I/O₆
I/O₁	14	19	I/O₅
I/O₂	15	18	I/O₄
GND	16	17	I/O₃

Pin	Symbol	Description
1	A₁₈	address input
2	A₁₆	address input
3	A₁₄	address input
4	A₁₂	address input
5	A₇	address input
6	A₆	address input
7	A₅	address input
8	A₄	address input
9	A₃	address input
10	A₂	address input
11	A₁	address input
12	A₀	address input
13	I/O₀	data input/output
14	I/O₁	data input/output
15	I/O₂	data input/output
16	GND	ground
17	I/O₃	data input/output
18	I/O₄	data input/output
19	I/O₅	data input/output
20	I/O₆	data input/output
21	I/O₇	data input/output
22	CS	chip select (active low)
23	A₁₀	address input
24	OE	output enable (active low)
25	A₁₁	address input
26	A₉	address input
27	A₈	address input
28	A₁₃	address input
29	WE	write enable (active low)
30	A₁₇	address input
31	A₁₅	address input
32	Vcc	supply voltage

Notes

Data is written when CS is low and WE is low.

Data is read when CS is low, OE is low, and WE is high.

The input/output pins assume a high-impedance state if CS is high.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

6581 - Sound Interface Device (SID) - msarnoff.org ChipDB

6581

Sound Interface Device (SID)


CAP1A	1 •	28	Vdd
CAP1B	2	27	AUDIO OUT
CAP2A	3	26	EXT IN
CAP2B	4	25	Vcc
RES	5	24	POTX
∅2	6	23	POTY
R/W	7	22	D7
CS	8	21	D6
A0	9	20	D5
A1	10	19	D4
A2	11	18	D3
A3	12	17	D2
A4	13	16	D1
GND	14	15	D0

Pin	Symbol	Description
1	CAP1A	capacitor C1 connection
2	CAP1B	capacitor C1 connection
3	CAP2A	capacitor C2 connection
4	CAP2B	capacitor C2 connection
5	RES	master reset
6	∅2	master clock
7	R/W	read/write select
8	CS	chip select (active low)
9	A0	address bus (register select)
10	A1	address bus (register select)
11	A2	address bus (register select)
12	A3	address bus (register select)
13	A4	address bus (register select)
14	GND	ground
15	D0	data bus
16	D1	data bus
17	D2	data bus
18	D3	data bus
19	D4	data bus
20	D5	data bus
21	D6	data bus
22	D7	data bus
23	POTY	Y-axis potentiometer input
24	POTX	X-axis potentiometer input
25	Vcc	+5VDC supply
26	EXT IN	external audio input
27	AUDIO OUT	audio output
28	Vdd	+12VDC supply

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Minimum clock cycle time	1	µs

Notes

C1 and C2 are integrating capacitors for the filter; polystyrene capacitors are preferred.

C1 and C2 should have the same value. 2200 pF gives good operation over the audio range (30Hz-12kHz).

Filter cutoff frequency is approx. 2.6×10^-5/C (where C is the value of C1 or C2).

POTX and POTY pins must be connected to RC networks; the time constant RC should be 4.7×10^-4. Recommended capacitor value is 1000 pF, recommended potentiometer value is 470 kΩ.

Maximum audio output level is approx. 3V p-p at a 6V DC level. A 1kΩ resistor should be connected from AUDIO OUT to ground, and a 1-10µF electrolytic capacitor should be used for AC coupling.

Registers:

$00	Voice 1 frequency low byte
$01	Voice 1 frequency high byte
$02	Voice 1 pulse width low byte
$03	Voice 1 pulse width high byte (bits 3-0)
$04	Voice 1 control (gate, sync, ring mod, waveform)
$05	Voice 1 attack/decay rates
$06	Voice 1 sustain level/release rate
$07	Voice 2 frequency low byte
$08	Voice 2 frequency high byte
$09	Voice 2 pulse width low byte
$0A	Voice 2 pulse width high byte (bits 3-0)
$0B	Voice 2 control (gate, sync, ring mod, waveform)
$0C	Voice 2 attack/decay rates
$0D	Voice 2 sustain level/release rate
$0E	Voice 3 frequency low byte
$0F	Voice 3 frequency high byte
$10	Voice 3 pulse width low byte
$11	Voice 3 pulse width high byte (bits 3-0)
$12	Voice 3 control (gate, sync, ring mod, waveform)
$13	Voice 3 attack/decay rates
$14	Voice 3 sustain level/release rate
$15	Filter cutoff frequency low byte
$16	Filter cutoff frequency high byte (bits 2-0)
$17	Filter resonance/control
$18	Filter mode/volume control
$19	POTX value (0-255), updated every 512 clock cycles
$1A	POTY value (0-255), updated every 512 clock cycles
$1B	Upper 8 bits of Oscillator 3 value (random number if noise waveform is selected)
$1C	Upper 8 bits of Voice 3 envelope generator value

Oscillator frequency = (Fn × Fclk/16777216) Hz

Pulse width = (PWn/40.95) %

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

6809E - 8-bit microprocessor - msarnoff.org ChipDB

6809E

8-bit microprocessor


Vss	1 •	40	HALT
NMI	2	39	TSC
IRQ	3	38	LIC
FIRQ	4	37	RESET
BS	5	36	AVMA
BA	6	35	Q
Vcc	7	34	E
A0	8	33	BUSY
A1	9	32	R/W
A2	10	31	D0
A3	11	30	D1
A4	12	29	D2
A5	13	28	D3
A6	14	27	D4
A7	15	26	D5
A8	16	25	D6
A9	17	24	D7
A10	18	23	A15
A11	19	22	A14
A12	20	21	A13

Pin	Symbol	Description
1	Vss	ground
2	NMI	non-maskable interrupt (active low)
3	IRQ	interrupt request (active low)
4	FIRQ	fast interrupt request (active low)
5	BS	bus status output
6	BA	bus available output
7	Vcc	supply voltage
8	A0	address bus
9	A1	address bus
10	A2	address bus
11	A3	address bus
12	A4	address bus
13	A5	address bus
14	A6	address bus
15	A7	address bus
16	A8	address bus
17	A9	address bus
18	A10	address bus
19	A11	address bus
20	A12	address bus
21	A13	address bus
22	A14	address bus
23	A15	address bus
24	D7	data bus
25	D6	data bus
26	D5	data bus
27	D4	data bus
28	D3	data bus
29	D2	data bus
30	D1	data bus
31	D0	data bus
32	R/W	bus read/write
33	BUSY	busy status
34	E	clock input
35	Q	quadrature clock input
36	AVMA	advanced VMA signal (indicates bus will be used in the next cycle)
37	RESET	reset (active low)
38	LIC	last instruction cycle (high during last cycle of instruction)
39	TSC	three-state control (active high; tri-states address, data, R/W)
40	HALT	halt (active low)

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Clock speed	1 (6809E) 1.5 (68A09E) 2 (68B09E)	MHz

Notes

Registers:

A, B	8-bit Accumulators (can be combined into 16-bit accumulator, D)
X	16-bit Index Register
Y	16-bit Index Register
U	16-bit User Stack Pointer
S	16-bit Hardware Stack Pointer
PC	16-bit Program Counter
DP	8-bit Direct Page Register
CC	8-bit Condition Code Register

Condition code bits: EFHINZVC

E	(bit 7)	Entire machine state was stacked
F	(bit 6)	FIRQ inhibit flag
H	(bit 5)	Half-carry flag (valid only after ADC or ADD instructions)
I	(bit 4)	IRQ inhibit flag
N	(bit 3)	Negative flag (most significant bit of previous result)
Z	(bit 2)	Zero flag
V	(bit 1)	Signed two's complement overflow flag
C	(bit 0)	Carry flag

CC	(pulled first, pushed last)
A
B
DP
X msb
X lsb
Y msb
Y lsb
U/S msb
U/S lsb
PC msb
PC lsb	(pulled last, pushed first)

Interrupt vectors:

FFFE-FFFF	RESET
FFFC-FFFD	NMI
FFFA-FFFB	SWI
FFF8-FFF9	IRQ
FFF6-FFF7	FIRQ
FFF4-FFF5	SWI2
FFF2-FFF3	SWI3
FFF1-FFF1	Reserved

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

6821 - Peripheral interface adapter - msarnoff.org ChipDB

6821

Peripheral interface adapter


GND	1 •	40	CA1
PA0	2	39	CA2
PA1	3	38	IRQA
PA2	4	37	IRQB
PA3	5	36	RS0
PA4	6	35	RS1
PA5	7	34	RESET
PA6	8	33	D0
PA7	9	32	D1
PB0	10	31	D2
PB1	11	30	D3
PB2	12	29	D4
PB3	13	28	D5
PB4	14	27	D6
PB5	15	26	D7
PB6	16	25	E
PB7	17	24	CS1
CB1	18	23	CS2
CB2	19	22	CS0
Vcc	20	21	R/W

Pin	Symbol	Description
1	GND	ground
2	PA0	port A
3	PA1	port A
4	PA2	port A
5	PA3	port A
6	PA4	port A
7	PA5	port A
8	PA6	port A
9	PA7	port A
10	PB0	port B
11	PB1	port B
12	PB2	port B
13	PB3	port B
14	PB4	port B
15	PB5	port B
16	PB6	port B
17	PB7	port B
18	CB1	peripheral control (port B)
19	CB2	peripheral control (port B)
20	Vcc	supply voltage
21	R/W	read/write
22	CS0	chip select (active high)
23	CS2	chip select (active low)
24	CS1	chip select (active high)
25	E	clock
26	D7	data bus
27	D6	data bus
28	D5	data bus
29	D4	data bus
30	D3	data bus
31	D2	data bus
32	D1	data bus
33	D0	data bus
34	RESET	master reset (active low)
35	RS1	register select (address bus)
36	RS0	register select (address bus)
37	IRQB	interrupt output (active low)
38	IRQA	interrupt output (active low)
39	CA2	peripheral control (port A)
40	CA1	peripheral control (port A)

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Max. clock frequency	1 (6821) 1.5 (68A21) 2 (68B21)	MHz
Pulse width, E low	430 (6821) 280 (68A21) 210 (68B21)	ns
Pulse width, E high	450 (6821) 280 (68A21) 220 (68B21)	ns
Min. RESET pulse length	1	µs

Notes

Port A is designed to drive CMOS logic to normal 30%/70% levels.

Port B uses three-state NMOS buffers and requires external resistors to pull up to CMOS levels.

Port B is capable of driving Darlingtons.

When in output mode, a read of Port A returns the actual pin states.

When in output mode, a read of Port B returns the contents of the output latch.

RS=00, bit 2 of control register A=1: peripheral register A

RS=00, bit 2 of control register A=0: data direction register A

RS=01: control register A

RS=10, bit 2 of control register B=1: peripheral register B

RS=10, bit 2 of control register B=0: data direction register B

RS=11: control register B

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

6809E - 8-bit microprocessor - msarnoff.org ChipDB

6809E

8-bit microprocessor


Vss	1 •	40	HALT
NMI	2	39	TSC
IRQ	3	38	LIC
FIRQ	4	37	RESET
BS	5	36	AVMA
BA	6	35	Q
Vcc	7	34	E
A0	8	33	BUSY
A1	9	32	R/W
A2	10	31	D0
A3	11	30	D1
A4	12	29	D2
A5	13	28	D3
A6	14	27	D4
A7	15	26	D5
A8	16	25	D6
A9	17	24	D7
A10	18	23	A15
A11	19	22	A14
A12	20	21	A13

Pin	Symbol	Description
1	Vss	ground
2	NMI	non-maskable interrupt (active low)
3	IRQ	interrupt request (active low)
4	FIRQ	fast interrupt request (active low)
5	BS	bus status output
6	BA	bus available output
7	Vcc	supply voltage
8	A0	address bus
9	A1	address bus
10	A2	address bus
11	A3	address bus
12	A4	address bus
13	A5	address bus
14	A6	address bus
15	A7	address bus
16	A8	address bus
17	A9	address bus
18	A10	address bus
19	A11	address bus
20	A12	address bus
21	A13	address bus
22	A14	address bus
23	A15	address bus
24	D7	data bus
25	D6	data bus
26	D5	data bus
27	D4	data bus
28	D3	data bus
29	D2	data bus
30	D1	data bus
31	D0	data bus
32	R/W	bus read/write
33	BUSY	busy status
34	E	clock input
35	Q	quadrature clock input
36	AVMA	advanced VMA signal (indicates bus will be used in the next cycle)
37	RESET	reset (active low)
38	LIC	last instruction cycle (high during last cycle of instruction)
39	TSC	three-state control (active high; tri-states address, data, R/W)
40	HALT	halt (active low)

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Clock speed	1 (6809E) 1.5 (68A09E) 2 (68B09E)	MHz

Notes

Registers:

A, B	8-bit Accumulators (can be combined into 16-bit accumulator, D)
X	16-bit Index Register
Y	16-bit Index Register
U	16-bit User Stack Pointer
S	16-bit Hardware Stack Pointer
PC	16-bit Program Counter
DP	8-bit Direct Page Register
CC	8-bit Condition Code Register

Condition code bits: EFHINZVC

E	(bit 7)	Entire machine state was stacked
F	(bit 6)	FIRQ inhibit flag
H	(bit 5)	Half-carry flag (valid only after ADC or ADD instructions)
I	(bit 4)	IRQ inhibit flag
N	(bit 3)	Negative flag (most significant bit of previous result)
Z	(bit 2)	Zero flag
V	(bit 1)	Signed two's complement overflow flag
C	(bit 0)	Carry flag

CC	(pulled first, pushed last)
A
B
DP
X msb
X lsb
Y msb
Y lsb
U/S msb
U/S lsb
PC msb
PC lsb	(pulled last, pushed first)

Interrupt vectors:

FFFE-FFFF	RESET
FFFC-FFFD	NMI
FFFA-FFFB	SWI
FFF8-FFF9	IRQ
FFF6-FFF7	FIRQ
FFF4-FFF5	SWI2
FFF2-FFF3	SWI3
FFF1-FFF1	Reserved

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

6821 - Peripheral interface adapter - msarnoff.org ChipDB

6821

Peripheral interface adapter


GND	1 •	40	CA1
PA0	2	39	CA2
PA1	3	38	IRQA
PA2	4	37	IRQB
PA3	5	36	RS0
PA4	6	35	RS1
PA5	7	34	RESET
PA6	8	33	D0
PA7	9	32	D1
PB0	10	31	D2
PB1	11	30	D3
PB2	12	29	D4
PB3	13	28	D5
PB4	14	27	D6
PB5	15	26	D7
PB6	16	25	E
PB7	17	24	CS1
CB1	18	23	CS2
CB2	19	22	CS0
Vcc	20	21	R/W

Pin	Symbol	Description
1	GND	ground
2	PA0	port A
3	PA1	port A
4	PA2	port A
5	PA3	port A
6	PA4	port A
7	PA5	port A
8	PA6	port A
9	PA7	port A
10	PB0	port B
11	PB1	port B
12	PB2	port B
13	PB3	port B
14	PB4	port B
15	PB5	port B
16	PB6	port B
17	PB7	port B
18	CB1	peripheral control (port B)
19	CB2	peripheral control (port B)
20	Vcc	supply voltage
21	R/W	read/write
22	CS0	chip select (active high)
23	CS2	chip select (active low)
24	CS1	chip select (active high)
25	E	clock
26	D7	data bus
27	D6	data bus
28	D5	data bus
29	D4	data bus
30	D3	data bus
31	D2	data bus
32	D1	data bus
33	D0	data bus
34	RESET	master reset (active low)
35	RS1	register select (address bus)
36	RS0	register select (address bus)
37	IRQB	interrupt output (active low)
38	IRQA	interrupt output (active low)
39	CA2	peripheral control (port A)
40	CA1	peripheral control (port A)

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Max. clock frequency	1 (6821) 1.5 (68A21) 2 (68B21)	MHz
Pulse width, E low	430 (6821) 280 (68A21) 210 (68B21)	ns
Pulse width, E high	450 (6821) 280 (68A21) 220 (68B21)	ns
Min. RESET pulse length	1	µs

Notes

Port A is designed to drive CMOS logic to normal 30%/70% levels.

Port B uses three-state NMOS buffers and requires external resistors to pull up to CMOS levels.

Port B is capable of driving Darlingtons.

When in output mode, a read of Port A returns the actual pin states.

When in output mode, a read of Port B returns the contents of the output latch.

RS=00, bit 2 of control register A=1: peripheral register A

RS=00, bit 2 of control register A=0: data direction register A

RS=01: control register A

RS=10, bit 2 of control register B=1: peripheral register B

RS=10, bit 2 of control register B=0: data direction register B

RS=11: control register B

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

6809E - 8-bit microprocessor - msarnoff.org ChipDB

6809E

8-bit microprocessor


Vss	1 •	40	HALT
NMI	2	39	TSC
IRQ	3	38	LIC
FIRQ	4	37	RESET
BS	5	36	AVMA
BA	6	35	Q
Vcc	7	34	E
A0	8	33	BUSY
A1	9	32	R/W
A2	10	31	D0
A3	11	30	D1
A4	12	29	D2
A5	13	28	D3
A6	14	27	D4
A7	15	26	D5
A8	16	25	D6
A9	17	24	D7
A10	18	23	A15
A11	19	22	A14
A12	20	21	A13

Pin	Symbol	Description
1	Vss	ground
2	NMI	non-maskable interrupt (active low)
3	IRQ	interrupt request (active low)
4	FIRQ	fast interrupt request (active low)
5	BS	bus status output
6	BA	bus available output
7	Vcc	supply voltage
8	A0	address bus
9	A1	address bus
10	A2	address bus
11	A3	address bus
12	A4	address bus
13	A5	address bus
14	A6	address bus
15	A7	address bus
16	A8	address bus
17	A9	address bus
18	A10	address bus
19	A11	address bus
20	A12	address bus
21	A13	address bus
22	A14	address bus
23	A15	address bus
24	D7	data bus
25	D6	data bus
26	D5	data bus
27	D4	data bus
28	D3	data bus
29	D2	data bus
30	D1	data bus
31	D0	data bus
32	R/W	bus read/write
33	BUSY	busy status
34	E	clock input
35	Q	quadrature clock input
36	AVMA	advanced VMA signal (indicates bus will be used in the next cycle)
37	RESET	reset (active low)
38	LIC	last instruction cycle (high during last cycle of instruction)
39	TSC	three-state control (active high; tri-states address, data, R/W)
40	HALT	halt (active low)

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Clock speed	1 (6809E) 1.5 (68A09E) 2 (68B09E)	MHz

Notes

Registers:

A, B	8-bit Accumulators (can be combined into 16-bit accumulator, D)
X	16-bit Index Register
Y	16-bit Index Register
U	16-bit User Stack Pointer
S	16-bit Hardware Stack Pointer
PC	16-bit Program Counter
DP	8-bit Direct Page Register
CC	8-bit Condition Code Register

Condition code bits: EFHINZVC

E	(bit 7)	Entire machine state was stacked
F	(bit 6)	FIRQ inhibit flag
H	(bit 5)	Half-carry flag (valid only after ADC or ADD instructions)
I	(bit 4)	IRQ inhibit flag
N	(bit 3)	Negative flag (most significant bit of previous result)
Z	(bit 2)	Zero flag
V	(bit 1)	Signed two's complement overflow flag
C	(bit 0)	Carry flag

CC	(pulled first, pushed last)
A
B
DP
X msb
X lsb
Y msb
Y lsb
U/S msb
U/S lsb
PC msb
PC lsb	(pulled last, pushed first)

Interrupt vectors:

FFFE-FFFF	RESET
FFFC-FFFD	NMI
FFFA-FFFB	SWI
FFF8-FFF9	IRQ
FFF6-FFF7	FIRQ
FFF4-FFF5	SWI2
FFF2-FFF3	SWI3
FFF1-FFF1	Reserved

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

6821 - Peripheral interface adapter - msarnoff.org ChipDB

6821

Peripheral interface adapter


GND	1 •	40	CA1
PA0	2	39	CA2
PA1	3	38	IRQA
PA2	4	37	IRQB
PA3	5	36	RS0
PA4	6	35	RS1
PA5	7	34	RESET
PA6	8	33	D0
PA7	9	32	D1
PB0	10	31	D2
PB1	11	30	D3
PB2	12	29	D4
PB3	13	28	D5
PB4	14	27	D6
PB5	15	26	D7
PB6	16	25	E
PB7	17	24	CS1
CB1	18	23	CS2
CB2	19	22	CS0
Vcc	20	21	R/W

Pin	Symbol	Description
1	GND	ground
2	PA0	port A
3	PA1	port A
4	PA2	port A
5	PA3	port A
6	PA4	port A
7	PA5	port A
8	PA6	port A
9	PA7	port A
10	PB0	port B
11	PB1	port B
12	PB2	port B
13	PB3	port B
14	PB4	port B
15	PB5	port B
16	PB6	port B
17	PB7	port B
18	CB1	peripheral control (port B)
19	CB2	peripheral control (port B)
20	Vcc	supply voltage
21	R/W	read/write
22	CS0	chip select (active high)
23	CS2	chip select (active low)
24	CS1	chip select (active high)
25	E	clock
26	D7	data bus
27	D6	data bus
28	D5	data bus
29	D4	data bus
30	D3	data bus
31	D2	data bus
32	D1	data bus
33	D0	data bus
34	RESET	master reset (active low)
35	RS1	register select (address bus)
36	RS0	register select (address bus)
37	IRQB	interrupt output (active low)
38	IRQA	interrupt output (active low)
39	CA2	peripheral control (port A)
40	CA1	peripheral control (port A)

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Max. clock frequency	1 (6821) 1.5 (68A21) 2 (68B21)	MHz
Pulse width, E low	430 (6821) 280 (68A21) 210 (68B21)	ns
Pulse width, E high	450 (6821) 280 (68A21) 220 (68B21)	ns
Min. RESET pulse length	1	µs

Notes

Port A is designed to drive CMOS logic to normal 30%/70% levels.

Port B uses three-state NMOS buffers and requires external resistors to pull up to CMOS levels.

Port B is capable of driving Darlingtons.

When in output mode, a read of Port A returns the actual pin states.

When in output mode, a read of Port B returns the contents of the output latch.

RS=00, bit 2 of control register A=1: peripheral register A

RS=00, bit 2 of control register A=0: data direction register A

RS=01: control register A

RS=10, bit 2 of control register B=1: peripheral register B

RS=10, bit 2 of control register B=0: data direction register B

RS=11: control register B

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

6N137 - 10 MBit/s single-channel high speed logic gate output optocoupler - msarnoff.org ChipDB
6N137
10 MBit/s single-channel high speed logic gate output optocoupler

N/C 1 • 8 Vcc
V_F + 2 7 V_E
V_F - 3 6 V_O
N/C 4 5 GND

Pin Symbol Description
1 N/C no connection
2 V_F + emitter, anode
3 V_F - emitter, cathode
4 N/C no connection
5 GND supply ground
6 V_O output
7 V_E enable input
8 Vcc supply voltage
Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Supply voltage, minimum 4.5 V
Supply voltage, maxmimum 5.5 V
Input forward voltage, typical @ 25C 1.4 V
Input forward voltage, typical @ 25C 1.4 V
Input forward voltage, max 1.8 V
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.
741 - Operational amplifier - msarnoff.org ChipDB
741
Operational amplifier

OFFSET NULL 1 • 8 NC
IN- 2 7 Vcc
IN+ 3 6 OUT
Vss 4 5 OFFSET NULL

Pin Symbol Description
1 OFFSET NULL offset null
2 IN- inverting input
3 IN+ non-inverting input
4 Vss negative supply voltage
5 OFFSET NULL offset null
6 OUT output
7 Vcc positive supply voltage
8 NC no connection
Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Supply voltage ±10 (min)
±22 (max) V
Maximum input voltage ±15 V
Gain bandwidth 1 MHz
Slew rate 0.5 V/µs
Supply current 1.7 mA

Notes
A 10 kΩ potentiometer connected to pins 1 and 5 can be used to null any offset voltage.
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

7400 - Quad 2-input NAND gate - msarnoff.org ChipDB

7400

Quad 2-input NAND gate


1A	1 •	14	Vcc
1B	2	13	4B
1Y	3	12	4A
2A	4	11	4Y
2B	5	10	3B
2Y	6	9	3A
GND	7	8	3Y

Pin	Symbol	Description
1	1A	data input
2	1B	data input
3	1Y	data output
4	2A	data input
5	2B	data input
6	2Y	data output
7	GND	ground
8	3Y	data output
9	3A	data input
10	3B	data input
11	4Y	data output
12	4A	data input
13	4B	data input
14	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nA, nB to nY	7 (74HC) 10 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

7402 - Quad 2-input NOR gate - msarnoff.org ChipDB

7402

Quad 2-input NOR gate


1Y	1 •	14	Vcc
1A	2	13	4Y
1B	3	12	4B
2Y	4	11	4A
2A	5	10	3Y
2B	6	9	3B
GND	7	8	3A

Pin	Symbol	Description
1	1Y	data output
2	1A	data input
3	1B	data input
4	2Y	data output
5	2A	data input
6	2B	data input
7	GND	ground
8	3A	data input
9	3B	data input
10	3Y	data output
11	4A	data input
12	4B	data input
13	4Y	data output
14	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nA, nB to nY	7 (74HC) 9 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

7404 - Hex inverter - msarnoff.org ChipDB

7404

Hex inverter


1A	1 •	14	Vcc
1Y	2	13	6A
2A	3	12	6Y
2Y	4	11	5A
3A	5	10	5Y
3Y	6	9	4A
GND	7	8	4Y

Pin	Symbol	Description
1	1A	data input
2	1Y	data output
3	2A	data input
4	2Y	data output
5	3A	data input
6	3Y	data output
7	GND	ground
8	4Y	data output
9	4A	data input
10	5Y	data output
11	5A	data input
12	6Y	data output
13	6A	data input
14	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nA to nY	7 (74HC) 8 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

7408 - Quad 2-input AND gate - msarnoff.org ChipDB

7408

Quad 2-input AND gate


1A	1 •	14	Vcc
1B	2	13	4B
1Y	3	12	4A
2A	4	11	4Y
2B	5	10	3B
2Y	6	9	3A
GND	7	8	3Y

Pin	Symbol	Description
1	1A	data input
2	1B	data input
3	1Y	data output
4	2A	data input
5	2B	data input
6	2Y	data output
7	GND	ground
8	3Y	data output
9	3A	data input
10	3B	data input
11	4Y	data output
12	4A	data input
13	4B	data input
14	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nA, nB to nY	7 (74HC) 11 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

7410 - Triple 3-input NAND gate - msarnoff.org ChipDB

7410

Triple 3-input NAND gate


1A	1 •	14	Vcc
1B	2	13	1C
2A	3	12	1Y
2B	4	11	3C
2C	5	10	3B
2Y	6	9	3A
GND	7	8	3Y

Pin	Symbol	Description
1	1A	data input
2	1B	data input
3	2A	data input
4	2B	data input
5	2C	data input
6	2Y	data output
7	GND	ground
8	3Y	data output
9	3A	data input
10	3B	data input
11	3C	data input
12	1Y	data output
13	1C	data input
14	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nA, nB, nC to nY	9 (74HC) 11 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

7411 - Triple 3-input AND gate - msarnoff.org ChipDB

7411

Triple 3-input AND gate


1A	1 •	14	Vcc
1B	2	13	1C
2A	3	12	1Y
2B	4	11	3C
2C	5	10	3B
2Y	6	9	3A
GND	7	8	3Y

Pin	Symbol	Description
1	1A	data input
2	1B	data input
3	2A	data input
4	2B	data input
5	2C	data input
6	2Y	data output
7	GND	ground
8	3Y	data output
9	3A	data input
10	3B	data input
11	3C	data input
12	1Y	data output
13	1C	data input
14	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nA, nB, nC to nY	10 (74HC) 11 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

7414 - Hex inverting Schmitt trigger - msarnoff.org ChipDB

7414

Hex inverting Schmitt trigger


1A	1 •	14	Vcc
1Y	2	13	6A
2A	3	12	6Y
2Y	4	11	5A
3A	5	10	5Y
3Y	6	9	4A
GND	7	8	4Y

Pin	Symbol	Description
1	1A	data input
2	1Y	data output
3	2A	data input
4	2Y	data output
5	3A	data input
6	3Y	data output
7	GND	ground
8	4Y	data output
9	4A	data input
10	5Y	data output
11	5A	data input
12	6Y	data output
13	6A	data input
14	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nA to nY	12 (74HC) 17 (74HCT)	ns
Positive-going threshold (Vcc = 4.5V)	2.38 (74HC) 1.41 (74HCT)	V
Negative-going threshold (Vcc = 4.5V)	1.4 (74HC) 0.85 (74HCT)	V
Hysteresis	0.98 (74HC) 0.56 (74HCT)	V

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

7420 - Dual 4-input NAND gate - msarnoff.org ChipDB

7420

Dual 4-input NAND gate


1A	1 •	14	Vcc
1B	2	13	2D
NC	3	12	2C
1C	4	11	NC
1D	5	10	2B
1Y	6	9	2A
GND	7	8	2Y

Pin	Symbol	Description
1	1A	data input
2	1B	data input
3	NC	no connection
4	1C	data input
5	1D	data input
6	1Y	data output
7	GND	ground
8	2Y	data output
9	2A	data input
10	2B	data input
11	NC	no connection
12	2C	data input
13	2D	data input
14	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nA, nB, nC, nD to nY	8 (74HC) 13 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

7421 - Dual 4-input AND gate - msarnoff.org ChipDB

7421

Dual 4-input AND gate


1A	1 •	14	Vcc
1B	2	13	2D
NC	3	12	2C
1C	4	11	NC
1D	5	10	2B
1Y	6	9	2A
GND	7	8	2Y

Pin	Symbol	Description
1	1A	data input
2	1B	data input
3	NC	no connection
4	1C	data input
5	1D	data input
6	1Y	data output
7	GND	ground
8	2Y	data output
9	2A	data input
10	2B	data input
11	NC	no connection
12	2C	data input
13	2D	data input
14	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nA, nB, nC, nD to nY	10 (74HC)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

7427 - Triple 3-input NOR gate - msarnoff.org ChipDB

7427

Triple 3-input NOR gate


1A	1 •	14	Vcc
1B	2	13	1C
2A	3	12	1Y
2B	4	11	3C
2C	5	10	3B
2Y	6	9	3A
GND	7	8	3Y

Pin	Symbol	Description
1	1A	data input
2	1B	data input
3	2A	data input
4	2B	data input
5	2C	data input
6	2Y	data output
7	GND	ground
8	3Y	data output
9	3A	data input
10	3B	data input
11	3C	data input
12	1Y	data output
13	1C	data input
14	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nA, nB, nC to nY	8 (74HC) 10 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

7430 - 8-input NAND gate - msarnoff.org ChipDB

7430

8-input NAND gate


A	1 •	14	Vcc
B	2	13	NC
C	3	12	H
D	4	11	G
E	5	10	NC
F	6	9	NC
GND	7	8	Y

Pin	Symbol	Description
1	A	data input
2	B	data input
3	C	data input
4	D	data input
5	E	data input
6	F	data input
7	GND	ground
8	Y	data output
9	NC	no connection
10	NC	no connection
11	G	data input
12	H	data input
13	NC	no connection
14	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, A, B, C, D, E, F, G, H, to Y	12 (74HC) 12 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

7432 - Quad 2-input OR gate - msarnoff.org ChipDB

7432

Quad 2-input OR gate


1A	1 •	14	Vcc
1B	2	13	4B
1Y	3	12	4A
2A	4	11	4Y
2B	5	10	3B
2Y	6	9	3A
GND	7	8	3Y

Pin	Symbol	Description
1	1A	data input
2	1B	data input
3	1Y	data output
4	2A	data input
5	2B	data input
6	2Y	data output
7	GND	ground
8	3Y	data output
9	3A	data input
10	3B	data input
11	4Y	data output
12	4A	data input
13	4B	data input
14	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nA, nB to nY	6 (74HC) 9 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74141 - BCD-to-decimal decoder/Nixie tube driver - msarnoff.org ChipDB
74141
BCD-to-decimal decoder/Nixie tube driver

8 1 • 16 0
9 2 15 1
A 3 14 5
D 4 13 4
Vcc 5 12 GND
B 6 11 6
C 7 10 7
2 8 9 3

Pin Symbol Description
1 8 output 8
2 9 output 9
3 A BCD input
4 D BCD input
5 Vcc supply voltage
6 B BCD input
7 C BCD input
8 2 output 2
9 3 output 3
10 7 output 7
11 6 output 6
12 GND ground
13 4 output 4
14 5 output 5
15 1 output 1
16 0 output 0

Notes
For binary inputs 10 through 15, behavior is manufacturer-specific. 7441s may enable one or more output. 74141s and K155ID1s will turn all outputs off, but the connected tube may not blank.
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.
7442 - BCD to decimal decoder (1-of-10) - msarnoff.org ChipDB
7442
BCD to decimal decoder (1-of-10)

Y₀ 1 • 16 Vcc
Y₁ 2 15 A₀
Y₂ 3 14 A₁
Y₃ 4 13 A₂
Y₄ 5 12 A₃
Y₅ 6 11 Y₉
Y₆ 7 10 Y₈
GND 8 9 Y₇

Pin Symbol Description
1 Y₀ output
2 Y₁ output
3 Y₂ output
4 Y₃ output
5 Y₄ output
6 Y₅ output
7 Y₆ output
8 GND ground
9 Y₇ output
10 Y₈ output
11 Y₉ output
12 A₃ data input
13 A₂ data input
14 A₁ data input
15 A₀ data input
16 Vcc supply voltage
Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
propagation delay, A_n to Y_n 14 (74HC)
17 (74HCT) ns
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

7458 - Dual AND-OR gate - msarnoff.org ChipDB

7458

Dual AND-OR gate


1A	1 •	14	Vcc
2A	2	13	1C
2B	3	12	1B
2C	4	11	1F
2D	5	10	1E
2Y	6	9	1D
GND	7	8	1Y

Pin	Symbol	Description
1	1A	data input
2	2A	data input
3	2B	data input
4	2C	data input
5	2D	data input
6	2Y	data output (2A · 2B) + (2C · 2D)
7	GND	ground
8	1Y	data output (1A · 1B · 1C) + (1D · 1E · 1F)
9	1D	data input
10	1E	data input
11	1F	data input
12	1B	data input
13	1C	data input
14	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, 1n to 1Y	11 (74HC)	ns
Propagation delay, 2n to 2Y	9 (74HC)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

7473 - Dual J-K flip-flop with reset; negative-edge trigger - msarnoff.org ChipDB

7473

Dual J-K flip-flop with reset; negative-edge trigger


1CP	1 •	14	1J
1R	2	13	1Q
1K	3	12	1Q
Vcc	4	11	GND
2CP	5	10	2K
2R	6	9	2Q
2J	7	8	2Q

Pin	Symbol	Description
1	1CP	clock input (high-to-low edge-triggered)
2	1R	asynchronous reset (active low)
3	1K	synchronous K input
4	Vcc	supply voltage
5	2CP	clock input (high-to-low edge-triggered)
6	2R	asynchronous reset (active low)
7	2J	synchronous J input
8	2Q	complement output
9	2Q	true output
10	2K	synchronous K input
11	GND	ground
12	1Q	true output
13	1Q	complement output
14	1J	synchronous J input

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nCP to nQ	16 (74HC)	ns
Propagation delay, nCP to nQ	16 (74HC)	ns
Propagation delay, nR to nQ, nQ	15 (74HC)	ns
Maximum frequency	77 (74HC)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

7474 - Dual D-type flip-flop with set and reset; positive-edge trigger - msarnoff.org ChipDB

7474

Dual D-type flip-flop with set and reset; positive-edge trigger


1RD	1 •	14	Vcc
1D	2	13	2RD
1CP	3	12	2D
1SD	4	11	2CP
1Q	5	10	2SD
1Q	6	9	2Q
GND	7	8	2Q

Pin	Symbol	Description
1	1RD	asynchronous reset-direct input (active low)
2	1D	data input
3	1CP	clock input (low-to-high edge-triggered)
4	1SD	asynchronous set-direct input (active low)
5	1Q	true output
6	1Q	complement output
7	GND	ground
8	2Q	complement output
9	2Q	true output
10	2SD	asynchronous set-direct input (active low)
11	2CP	clock input (low-to-high edge-triggered)
12	2D	data input
13	2RD	asynchronous reset-direct input (active low)
14	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nCP to nQ, nQ	14 (74HC) 15 (74HCT)	ns
Propagation delay, nSD to nQ, nQ	15 (74HC) 18 (74HCT)	ns
Propagation delay, nRD to nQ, nQ	16 (74HC) 18 (74HCT)	ns
Maximum clock frequency	76 (74HC) 59 (74HCT)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

7475 - Quad bistable transparent latch - msarnoff.org ChipDB

7475

Quad bistable transparent latch


1Q	1 •	16	1Q
1D	2	15	2Q
2D	3	14	2Q
LE34	4	13	LE12
Vcc	5	12	GND
3D	6	11	3Q
4D	7	10	3Q
4Q	8	9	4Q

Pin	Symbol	Description
1	1Q	complementary latch output 1
2	1D	data input 1
3	2D	data input 2
4	LE34	latch enable input for latches 3 and 4
5	Vcc	supply voltage
6	3D	data input 3
7	4D	data input 4
8	4Q	complementary latch output 4
9	4Q	latch output 4
10	3Q	latch output 3
11	3Q	complementary latch output 3
12	GND	ground
13	LE12	latch enable input for latches 1 and 2
14	2Q	complementary latch output 2
15	2Q	latch output 2
16	1Q	latch output 1

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay	11 (74HC)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

7485 - 4-bit magnitude comparator - msarnoff.org ChipDB

7485

4-bit magnitude comparator


B₃	1 •	16	Vcc
I_A<B	2	15	A₃
I_A=B	3	14	B₂
I_A>B	4	13	A₂
Q_A>B	5	12	A₁
Q_A=B	6	11	B₁
Q_A<B	7	10	A₀
GND	8	9	B₀

Pin	Symbol	Description
1	B₃	word B input
2	I_A<B	A < B expansion input
3	I_A=B	A = B expansion input
4	I_A>B	A > B expansion input
5	Q_A>B	A > B output
6	Q_A=B	A = B output
7	Q_A<B	A < B output
8	GND	ground
9	B₀	word B input
10	A₀	word A input
11	B₁	word B input
12	A₁	word A input
13	A₂	word A input
14	B₂	word B input
15	A₃	word A input
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, A_n, B_n to Q_A>B, Q_A<B	20 (74HC) 22 (74HCT)	ns
Propagation delay, A_n, B_n to Q_A=B	18 (74HC) 20 (74HCT)	ns
Propagation delay, I_A<B, I_A=B, I_A>B to Q_A<B, Q_A>B	15 (74HC) 15 (74HCT)	ns
Propagation delay, I_A=B to Q_A=B	11 (74HC) 15 (74HCT)	ns

Notes

The least significant (or only) comparator in a chain should have I_A<B and I_A>B tied low and I_A=B tied high.

To compare more than 4 bits, connect the outputs to the expansion inputs of the next significant comparator.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

7486 - Quad 2-input XOR gate - msarnoff.org ChipDB

7486

Quad 2-input XOR gate


1A	1 •	14	Vcc
1B	2	13	4B
1Y	3	12	4A
2A	4	11	4Y
2B	5	10	3B
2Y	6	9	3A
GND	7	8	3Y

Pin	Symbol	Description
1	1A	data input
2	1B	data input
3	1Y	data output
4	2A	data input
5	2B	data input
6	2Y	data output
7	GND	ground
8	3Y	data output
9	3A	data input
10	3B	data input
11	4Y	data output
12	4A	data input
13	4B	data input
14	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nA, nB to nY	11 (74HC) 14 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

7490 - 4-bit decade counter - msarnoff.org ChipDB

7490

4-bit decade counter


CKB	1 •	14	CKA
R0(1)	2	13	NC
R0(2)	3	12	Q_A
NC	4	11	Q_D
Vcc	5	10	GND
R9(1)	6	9	Q_B
R9(2)	7	8	Q_C

Pin	Symbol	Description
1	CKB	clock input
2	R0(1)	reset to 0
3	R0(2)	reset to 0
4	NC	no connection
5	Vcc	supply voltage
6	R9(1)	reset to 9
7	R9(2)	reset to 9
8	Q_C	counter output
9	Q_B	counter output
10	GND	ground
11	Q_D	counter output
12	Q_A	counter output
13	NC	no connection
14	CKA	clock input

Notes

For maximum count length, connect CKB to Q_A and apply input pulses to CKA.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

7493 - 4-bit binary ripple counter - msarnoff.org ChipDB

7493

4-bit binary ripple counter


CP₁	1 •	14	CP₀
MR₁	2	13	NC
MR₂	3	12	Q₀
NC	4	11	Q₃
Vcc	5	10	GND
NC	6	9	Q₁
NC	7	8	Q₂

Pin	Symbol	Description
1	CP₁	clock input, 2nd, 3rd and 4th section (high-to-low edge-triggered)
2	MR₁	asynchronous master reset
3	MR₂	asynchronous master reset
4	NC	no connection
5	Vcc	supply voltage
6	NC	no connection
7	NC	no connection
8	Q₂	counter output
9	Q₁	counter output
10	GND	ground
11	Q₃	counter output
12	Q₀	counter output
13	NC	no connection
14	CP₀	clock input, 1st section (high-to-low edge-triggered)

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CP₀ to Q₀	12 (74HC) 15 (74HCT)	ns
Maximum clock frequency	100 (74HC) 77 (74HCT)	MHz

Notes

State changes of Q_n outputs do not occur simultaneously.

Setting both MR₁ and MR₂ high resets the counter to zero.

For a 4-bit counter, connect Q₀ to CP₁, and apply count pulses to CP₀.

For a 3-bit counter, apply count pulses to CP₁.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74107 - Dual J-K flip-flop with reset; negative-edge trigger - msarnoff.org ChipDB

74107

Dual J-K flip-flop with reset; negative-edge trigger


1J	1 •	14	Vcc
1Q	2	13	1R
1Q	3	12	1CP
1K	4	11	2K
2Q	5	10	2R
2Q	6	9	2CP
GND	7	8	2J

Pin	Symbol	Description
1	1J	synchronous input
2	1Q	complement output
3	1Q	true output
4	1K	synchronous input
5	2Q	true output
6	2Q	complement output
7	GND	ground
8	2J	synchronous input
9	2CP	clock input (high-to-low, edge-triggered)
10	2R	asynchronous reset (active low)
11	2K	synchronous input
12	1CP	clock input (high-to-low, edge-triggered)
13	1R	asynchronous reset (active low)
14	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nCP to nQ	16 (74HC) 16 (74HCT)	ns
Propagation delay, nCP to nQ	16 (74HC) 18 (74HCT)	ns
Propagation delay, nR to nQ, nQ	16 (74HC) 17 (74HCT)	ns
Maximum clock frequency	78 (74HC) 73 (74HCT)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74109 - Dual J-K flip-flop with set and reset; positive-edge trigger - msarnoff.org ChipDB

74109

Dual J-K flip-flop with set and reset; positive-edge trigger


1R_D	1 •	16	Vcc
1J	2	15	2R_D
1K	3	14	2J
1CP	4	13	2K
1S_D	5	12	2CP
1Q	6	11	2S_D
1Q	7	10	2Q
GND	8	9	2Q

Pin	Symbol	Description
1	1R_D	asynchronous reset; direct input (active low)
2	1J	synchronous input
3	1K	synchronous input
4	1CP	clock input (low-to-high, edge-triggered)
5	1S_D	asynchronous set; direct input (active low)
6	1Q	true output
7	1Q	complement output
8	GND	ground
9	2Q	complement output
10	2Q	true output
11	2S_D	asynchronous set; direct input (active low)
12	2CP	clock input (low-to-high, active low)
13	2K	synchronous input
14	2J	synchronous input
15	2R_D	asynchronous reset; direct input (active low)
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nCP to nQ, nQ	15 (74HC) 17 (74HCT)	ns
Propagation delay, nS_D to nQ, nQ	12 (74HC) 14 (74HCT)	ns
Propagation delay, nR_D to nQ, nQ	12 (74HC) 15 (74HCT)	ns
Maximum clock frequency	75 (74HC) 61 (74HCT)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74112 - Dual J-K flip-flop with set and reset; negative-edge trigger - msarnoff.org ChipDB

74112

Dual J-K flip-flop with set and reset; negative-edge trigger


1CP	1 •	16	Vcc
1K	2	15	1R_D
1J	3	14	2R_D
1S_D	4	13	2CP
1Q	5	12	2K
1Q	6	11	2J
2Q	7	10	2S_D
GND	8	9	2Q

Pin	Symbol	Description
1	1CP	clock input (high-to-low, edge-triggered)
2	1K	synchronous input
3	1J	synchronous input
4	1S_D	asynchronous set; direct input (active low)
5	1Q	true output
6	1Q	complement output
7	2Q	complement output
8	GND	ground
9	2Q	true output
10	2S_D	asynchronous set; direct input (active low)
11	2J	synchronous input
12	2K	synchronous input
13	2CP	clock input (high-to-low, edge-triggered)
14	2R_D	asynchronous reset; direct input (active low)
15	1R_D	asynchronous reset; direct input (active low)
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nCP to nQ, nQ	17 (74HC) 19 (74HCT)	ns
Propagation delay, nS_D to nQ, nQ	15 (74HC) 15 (74HCT)	ns
Propagation delay, nR_D to nQ, nQ	18 (74HC) 19 (74HCT)	ns
Maximum clock frequency	66 (74HC) 70 (74HCT)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74123 - Dual retriggerable monostable multivibrator with reset - msarnoff.org ChipDB

74123

Dual retriggerable monostable multivibrator with reset


1A	1 •	16	Vcc
1B	2	15	1REXT/CEXT
1RD	3	14	1CEXT
1Q	4	13	1Q
2Q	5	12	2Q
2CEXT	6	11	2RD
2REXT/CEXT	7	10	2B
GND	8	9	2A

Pin	Symbol	Description
1	1A	negative-edge triggered input 1
2	1B	positive-edge triggered input 1
3	1RD	direct reset (active low) and positive-edge triggered input 1
4	1Q	active low output 1
5	2Q	active high output 2
6	2CEXT	external capacitor connection 2
7	2REXT/CEXT	external resistor and capacitor connection 2
8	GND	ground
9	2A	negative-edge triggered input 2
10	2B	positive-edge triggered input 2
11	2RD	direct reset (active low) and positive-edge triggered input 2
12	2Q	active low output 2
13	1Q	active high output 1
14	1CEXT	external capacitor connection 1
15	1REXT/CEXT	external resistor and capacitor connection 1
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nRD, nA, nB to nQ or nQ	26 (74HC/HCT)	ns
Propagation delay, nRD to nQ or nQ	20 (74HC) 23 (74HCT)	ns
Output transition time	7 (74HC/HCT)	ns
Retrigger time nA, nB	110 (74HC/HCT)	ns
External timing resistor	2 (min) 1000 (max)	kΩ

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74125 - Quad buffer/line driver with active low output enable; 3-state - msarnoff.org ChipDB

74125

Quad buffer/line driver with active low output enable; 3-state


1OE	1 •	14	Vcc
1A	2	13	4OE
1Y	3	12	4A
2OE	4	11	4Y
2A	5	10	3OE
2Y	6	9	3A
GND	7	8	3Y

Pin	Symbol	Description
1	1OE	output enable (active low)
2	1A	data input
3	1Y	data output
4	2OE	output enable (active low)
5	2A	data input
6	2Y	data output
7	GND	ground
8	3Y	data output
9	3A	data input
10	3OE	output enable (active low)
11	4Y	data output
12	4A	data input
13	4OE	output enable (active low)
14	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nA to nY	9 (74HC) 12 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74126 - Quad buffer/line driver with active high output enable; 3-state - msarnoff.org ChipDB

74126

Quad buffer/line driver with active high output enable; 3-state


1OE	1 •	14	Vcc
1A	2	13	4OE
1Y	3	12	4A
2OE	4	11	4Y
2A	5	10	3OE
2Y	6	9	3A
GND	7	8	3Y

Pin	Symbol	Description
1	1OE	output enable (active high)
2	1A	data input
3	1Y	data output
4	2OE	output enable (active high)
5	2A	data input
6	2Y	data output
7	GND	ground
8	3Y	data output
9	3A	data input
10	3OE	output enable (active high)
11	4Y	data output
12	4A	data input
13	4OE	output enable (active high)
14	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nA to nY	9 (74HC) 11 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74132 - Quad 2-input NAND Schmitt trigger - msarnoff.org ChipDB

74132

Quad 2-input NAND Schmitt trigger


1A	1 •	14	Vcc
1B	2	13	4B
1Y	3	12	4A
2A	4	11	4Y
2B	5	10	3B
2Y	6	9	3A
GND	7	8	3Y

Pin	Symbol	Description
1	1A	data input
2	1B	data input
3	1Y	data output
4	2A	data input
5	2B	data input
6	2Y	data output
7	GND	ground
8	3Y	data output
9	3A	data input
10	3B	data input
11	4Y	data output
12	4A	data input
13	4B	data input
14	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nA, nB to nY	10 (74HC) 17 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74137 - 3-to-8 line decoder/demultiplexer with address latches; inverting - msarnoff.org ChipDB

74137

3-to-8 line decoder/demultiplexer with address latches; inverting


A0	1 •	16	Vcc
A1	2	15	Y0
A2	3	14	Y1
LE	4	13	Y2
E1	5	12	Y3
E2	6	11	Y4
Y7	7	10	Y5
GND	8	9	Y6

Pin	Symbol	Description
1	A0	data input 0
2	A1	data input 1
3	A2	data input 2
4	LE	latch enable input (active low)
5	E1	data enable input 1 (active low)
6	E2	data enable input 2 (active high)
7	Y7	output 7
8	GND	ground
9	Y6	output 6
10	Y5	output 5
11	Y4	output 4
12	Y3	output 3
13	Y2	output 2
14	Y1	output 1
15	Y0	output 0
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, An to Yn	18 (74HC)	ns
Propagation delay, LE to Yn	17 (74HC)	ns
Propagation delay, E1 to Yn	15 (74HC)	ns
Propagation delay, E2 to Yn	15 (74HC)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74138 - 3-to-8 line decoder/demultiplexer; inverting - msarnoff.org ChipDB

74138

3-to-8 line decoder/demultiplexer; inverting


A0	1 •	16	Vcc
A1	2	15	Y0
A2	3	14	Y1
E1	4	13	Y2
E2	5	12	Y3
E3	6	11	Y4
Y7	7	10	Y5
GND	8	9	Y6

Pin	Symbol	Description
1	A0	data input 0
2	A1	data input 1
3	A2	data input 2
4	E1	enable input 1 (active low)
5	E2	enable input 2 (active low)
6	E3	enable input 3 (active high)
7	Y7	output 7
8	GND	ground
9	Y6	output 6
10	Y5	output 5
11	Y4	output 4
12	Y3	output 3
13	Y2	output 2
14	Y1	output 1
15	Y0	output 0
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, An to Yn	12 (74HC) 17 (74HCT)	ns
Propagation delay, E3 to Yn	14 (74HC) 19 (74HCT)	ns
Propagation delay, En to Yn	14 (74HC) 19 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74139 - Dual 2-to-4 line decoder/demultiplexer - msarnoff.org ChipDB

74139

Dual 2-to-4 line decoder/demultiplexer


1E	1 •	16	Vcc
1A₀	2	15	2E
1A₁	3	14	2A₀
1Y₀	4	13	2A₁
1Y₁	5	12	2Y₀
1Y₂	6	11	2Y₁
1Y₃	7	10	2Y₂
GND	8	9	2Y₃

Pin	Symbol	Description
1	1E	enable input (active low)
2	1A₀	address input
3	1A₁	address input
4	1Y₀	output (active low)
5	1Y₁	output (active low)
6	1Y₂	output (active low)
7	1Y₃	output (active low)
8	GND	ground
9	2Y₃	output (active low)
10	2Y₂	output (active low)
11	2Y₁	output (active low)
12	2Y₀	output (active low)
13	2A₁	address input
14	2A₀	address input
15	2E	enable input (active low)
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nA_n to nY_n	11 (74HC) 13 (74HCT)	ns
Propagation delay, nE to nY_n	10 (74HC) 13 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74141 - BCD-to-decimal decoder/Nixie tube driver - msarnoff.org ChipDB
74141
BCD-to-decimal decoder/Nixie tube driver

8 1 • 16 0
9 2 15 1
A 3 14 5
D 4 13 4
Vcc 5 12 GND
B 6 11 6
C 7 10 7
2 8 9 3

Pin Symbol Description
1 8 output 8
2 9 output 9
3 A BCD input
4 D BCD input
5 Vcc supply voltage
6 B BCD input
7 C BCD input
8 2 output 2
9 3 output 3
10 7 output 7
11 6 output 6
12 GND ground
13 4 output 4
14 5 output 5
15 1 output 1
16 0 output 0

Notes
For binary inputs 10 through 15, behavior is manufacturer-specific. 7441s may enable one or more output. 74141s and K155ID1s will turn all outputs off, but the connected tube may not blank.
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74147 - 10-to-4 line priority encoder - msarnoff.org ChipDB

74147

10-to-4 line priority encoder


A₃	1 •	16	Vcc
A₄	2	15	NC
A₅	3	14	Y₃
A₆	4	13	A₂
A₇	5	12	A₁
Y₂	6	11	A₀
Y₁	7	10	A₈
GND	8	9	Y₀

Pin	Symbol	Description
1	A₃	decimal data input (active low)
2	A₄	decimal data input (active low)
3	A₅	decimal data input (active low)
4	A₆	decimal data input (active low)
5	A₇	decimal data input (active low)
6	Y₂	BCD address output (active low)
7	Y₁	BCD address output (active low)
8	GND	ground
9	Y₀	BCD address output (active low)
10	A₈	decimal data input (active low)
11	A₀	decimal data input (active low)
12	A₁	decimal data input (active low)
13	A₂	decimal data input (active low)
14	Y₃	BCD address output (active low)
15	NC	no connection
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, A_n to Y_n	15 (74HC) 17 (74HCT)	ns

Notes

When two or more inputs are simultaneously active, the input with the highest priority is represented on the output.

A₈ has the highest priority.

When all nine data inputs are high, all four outputs are high. (BCD zero)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74148 - 8-to-3 line priority encoder - msarnoff.org ChipDB

74148

8-to-3 line priority encoder


4	1 •	16	Vcc
5	2	15	EO
6	3	14	GS
7	4	13	3
EI	5	12	2
A2	6	11	1
A1	7	10	0
GND	8	9	A0

Pin	Symbol	Description
1	4	decimal data input (active low)
2	5	decimal data input (active low)
3	6	decimal data input (active low)
4	7	decimal data input (active low)
5	EI	enable input (active low)
6	A2	binary address output (active low)
7	A1	BCD address output (active low)
8	GND	ground
9	A0	binary address output (active low)
10	0	decimal data input (active low)
11	1	decimal data input (active low)
12	2	decimal data input (active low)
13	3	decimal data input (active low)
14	GS	goes low when EI is low and any input is low
15	EO	goes high when EI is low and any input is low (EO = GS)
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, n to An	16 (74HC)	ns

Notes

When two or more inputs are simultaneously active, the input with the highest priority is represented on the output.

Input 7 has the highest priority.

When all eight data inputs are high, all three outputs are high.

Multiple 74148s can be cascaded by connecting EO of the high priority chip to EI of the low priority chip (see datasheet).

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74151 - 8-input multiplexer - msarnoff.org ChipDB

74151

8-input multiplexer


I₃	1 •	16	Vcc
I₂	2	15	I₄
I₁	3	14	I₅
I₀	4	13	I₆
Y	5	12	I₇
Y	6	11	S₀
E	7	10	S₁
GND	8	9	S₂

Pin	Symbol	Description
1	I₃	multiplexer input
2	I₂	multiplexer input
3	I₁	multiplexer input
4	I₀	multiplexer input
5	Y	multiplexer output
6	Y	complementary multiplexer output
7	E	enable input (active low)
8	GND	ground
9	S₂	select input
10	S₁	select input
11	S₀	select input
12	I₇	multiplexer input
13	I₆	multiplexer input
14	I₅	multiplexer input
15	I₄	multiplexer input
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, I_n to Y, Y	17 (74HC) 19 (74HCT)	ns
Propagation delay, S_n to Y, Y	19 (74HC) 20 (74HCT)	ns
Propagation delay, E to Y	12 (74HC) 13 (74HCT)	ns
Propagation delay, E to Y	14 (74HC) 18 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74153 - Dual 4-input multiplexer - msarnoff.org ChipDB

74153

Dual 4-input multiplexer


1E	1 •	16	Vcc
S₁	2	15	2E
1I₃	3	14	S₀
1I₂	4	13	2I₃
1I₁	5	12	2I₂
1I₀	6	11	2I₁
1Y	7	10	2I₀
GND	8	9	2Y

Pin	Symbol	Description
1	1E	enable input 1
2	S₁	common data select input
3	1I₃	data input from source 1
4	1I₂	data input from source 1
5	1I₁	data input from source 1
6	1I₀	data input from source 1
7	1Y	multiplexer output from source 1
8	GND	ground
9	2Y	multiplexer output from source 2
10	2I₀	data input from source 2
11	2I₁	data input from source 2
12	2I₂	data input from source 2
13	2I₃	data input from source 2
14	S₀	common data select input
15	2E	enable input 2
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, 1I_n, 2I_n to nY	14 (74HC) 16 (74HCT)	ns
Propagation delay, S_n to nY	15 (74HC) 17 (74HCT)	ns
Propagation delay, nE to nY	10 (74HC) 11 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74154 - 4-to-16 line decoder/demultiplexer - msarnoff.org ChipDB

74154

4-to-16 line decoder/demultiplexer


Y0	1 •	24	Vcc
Y1	2	23	A0
Y2	3	22	A1
Y3	4	21	A2
Y4	5	20	A3
Y5	6	19	E1
Y6	7	18	E0
Y7	8	17	Y15
Y8	9	16	Y14
Y9	10	15	Y13
Y10	11	14	Y12
GND	12	13	Y11

Pin	Symbol	Description
1	Y0	data output (active low)
2	Y1	data output (active low)
3	Y2	data output (active low)
4	Y3	data output (active low)
5	Y4	data output (active low)
6	Y5	data output (active low)
7	Y6	data output (active low)
8	Y7	data output (active low)
9	Y8	data output (active low)
10	Y9	data output (active low)
11	Y10	data output (active low)
12	GND	ground
13	Y11	data output (active low)
14	Y12	data output (active low)
15	Y13	data output (active low)
16	Y14	data output (active low)
17	Y15	data output (active low)
18	E0	enable input (active low)
19	E1	enable input (active low)
20	A3	address input
21	A2	address input
22	A1	address input
23	A0	address input
24	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, An to Yn	11 (74HC) 13 (74HCT)	ns
Propagation delay, En to Yn	11 (74HC) 13 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74157 - Quad 2-input multiplexer - msarnoff.org ChipDB

74157

Quad 2-input multiplexer


S	1 •	16	Vcc
1I₀	2	15	E
1I₁	3	14	4I₀
1Y	4	13	4I₁
2I₀	5	12	4Y
2I₁	6	11	3I₀
2Y	7	10	3I₁
GND	8	9	3Y

Pin	Symbol	Description
1	S	common data select input
2	1I₀	data input from source 0
3	1I₁	data input from source 1
4	1Y	multiplexer output
5	2I₀	data input from source 0
6	2I₁	data input from source 1
7	2Y	multiplexer output
8	GND	ground
9	3Y	multiplexer output
10	3I₁	data input from source 1
11	3I₀	data input from source 0
12	4Y	multiplexer output
13	4I₁	data input from source 1
14	4I₀	data input from source 0
15	E	enable input (active low)
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nI₀, nI₁ to nY	11 (74HC) 13 (74HCT)	ns
Propagation delay, E to nY	11 (74HC) 12 (74HCT)	ns
Propagation delay, S to nY	12 (74HC) 19 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74158 - Quad 2-input multiplexer; inverting - msarnoff.org ChipDB

74158

Quad 2-input multiplexer; inverting


S	1 •	16	Vcc
1I₀	2	15	E
1I₁	3	14	4I₀
1Y	4	13	4I₁
2I₀	5	12	4Y
2I₁	6	11	3I₀
2Y	7	10	3I₁
GND	8	9	3Y

Pin	Symbol	Description
1	S	common data select input
2	1I₀	data input from source 0
3	1I₁	data input from source 1
4	1Y	multiplexer output
5	2I₀	data input from source 0
6	2I₁	data input from source 1
7	2Y	multiplexer output
8	GND	ground
9	3Y	multiplexer output
10	3I₁	data input from source 1
11	3I₀	data input from source 0
12	4Y	multiplexer output
13	4I₁	data input from source 1
14	4I₀	data input from source 0
15	E	enable input (active low)
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nI₀, nI₁ to nY	12 (74HC)	ns
Propagation delay, E to nY	14 (74HC)	ns
Propagation delay, S to nY	14 (74HC)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74160 - Presettable synchronous BCD decade counter; asynchronous reset - msarnoff.org ChipDB

74160

Presettable synchronous BCD decade counter; asynchronous reset


MR	1 •	16	Vcc
CP	2	15	TC
D₀	3	14	Q₀
D₁	4	13	Q₁
D₂	5	12	Q₂
D₃	6	11	Q₃
CEP	7	10	CET
GND	8	9	PE

Pin	Symbol	Description
1	MR	asynchronous master reset (active low)
2	CP	clock input (low-to-high, edge-triggered)
3	D₀	data input
4	D₁	data input
5	D₂	data input
6	D₃	data input
7	CEP	count enable input
8	GND	ground
9	PE	parallel load enable input (active low)
10	CET	count enable carry output
11	Q₃	counter output
12	Q₂	counter output
13	Q₁	counter output
14	Q₀	counter output
15	TC	terminal count output
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CP to Q_n	19 (74HC) 21 (74HCT)	ns
Propagation delay, CP to TC	21 (74HC) 24 (74HCT)	ns
Propagation delay, MR to Q_n	21 (74HC) 23 (74HCT)	ns
Propagation delay, MR to TC	21 (74HC) 26 (74HCT)	ns
Propagation delay, CET to TC	14 (74HC) 14 (74HCT)	ns
Maximum clock frequency	61 (74HC) 31 (74HCT)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74161 - Presettable synchronous 4-bit binary counter; asynchronous reset - msarnoff.org ChipDB

74161

Presettable synchronous 4-bit binary counter; asynchronous reset


MR	1 •	16	Vcc
CP	2	15	TC
D₀	3	14	Q₀
D₁	4	13	Q₁
D₂	5	12	Q₂
D₃	6	11	Q₃
CEP	7	10	CET
GND	8	9	PE

Pin	Symbol	Description
1	MR	asynchronous master reset (active low)
2	CP	clock input (low-to-high, edge-triggered)
3	D₀	data input
4	D₁	data input
5	D₂	data input
6	D₃	data input
7	CEP	count enable input
8	GND	ground
9	PE	parallel load enable input (active low)
10	CET	count enable carry output
11	Q₃	counter output
12	Q₂	counter output
13	Q₁	counter output
14	Q₀	counter output
15	TC	terminal count output
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CP to Q_n	19 (74HC) 20 (74HCT)	ns
Propagation delay, CP to TC	21 (74HC) 24 (74HCT)	ns
Propagation delay, MR to Q_n	20 (74HC) 25 (74HCT)	ns
Propagation delay, MR to TC	20 (74HC) 26 (74HCT)	ns
Propagation delay, CET to TC	10 (74HC) 14 (74HCT)	ns
Maximum clock frequency	44 (74HC) 45 (74HCT)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74163 - Presettable synchronous 4-bit binary counter; synchronous reset - msarnoff.org ChipDB

74163

Presettable synchronous 4-bit binary counter; synchronous reset


MR	1 •	16	Vcc
CP	2	15	TC
D₀	3	14	Q₀
D₁	4	13	Q₁
D₂	5	12	Q₂
D₃	6	11	Q₃
CEP	7	10	CET
GND	8	9	PE

Pin	Symbol	Description
1	MR	synchronous master reset (active low)
2	CP	clock input (low-to-high, edge-triggered)
3	D₀	data input
4	D₁	data input
5	D₂	data input
6	D₃	data input
7	CEP	count enable input
8	GND	ground
9	PE	parallel load enable input (active low)
10	CET	count enable carry output
11	Q₃	counter output
12	Q₂	counter output
13	Q₁	counter output
14	Q₀	counter output
15	TC	terminal count output
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CP to Q_n	17 (74HC) 20 (74HCT)	ns
Propagation delay, CP to TC	21 (74HC) 25 (74HCT)	ns
Propagation delay, CET to TC	11 (74HC) 14 (74HCT)	ns
Maximum clock frequency	51 (74HC) 50 (74HCT)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74164 - 8-bit serial-in/parallel-out shift register - msarnoff.org ChipDB

74164

8-bit serial-in/parallel-out shift register


DSA	1 •	14	Vcc
DSB	2	13	Q7
Q0	3	12	Q6
Q1	4	11	Q5
Q2	5	10	Q4
Q3	6	9	MR
GND	7	8	CP

Pin	Symbol	Description
1	DSA	data input
2	DSB	data input
3	Q0	output
4	Q1	output
5	Q2	output
6	Q3	output
7	GND	ground
8	CP	clock input (low-to-high, edge-triggered)
9	MR	master reset input (active low)
10	Q4	output
11	Q5	output
12	Q6	output
13	Q7	output
14	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CP to Qn	12 (74HC) 14 (74HCT)	ns
Propagation delay, MR to Qn	11 (74HC) 16 (74HCT)	ns
Maximum clock frequency	78 (74HC) 61 (74HCT)	MHz

Notes

Either DSA or DSB can be used as an active high enable for data entry through the other input.

Otherwise, Both inputs must be connected together or an unused input must be tied high.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74165 - 8-bit parallel-in/serial-out shift register - msarnoff.org ChipDB

74165

8-bit parallel-in/serial-out shift register


PL	1 •	16	Vcc
CP	2	15	CE
D4	3	14	D3
D5	4	13	D2
D6	5	12	D1
D7	6	11	D0
Q7	7	10	DS
GND	8	9	Q7

Pin	Symbol	Description
1	PL	asynchronous parallel load input (active low)
2	CP	clock input (low-to-high, edge-triggered)
3	D4	parallel data input
4	D5	parallel data input
5	D6	parallel data input
6	D7	parallel data input
7	Q7	complementary output from the last stage
8	GND	ground
9	Q7	serial output from the last stage
10	DS	serial data input
11	D0	parallel data input
12	D1	parallel data input
13	D2	parallel data input
14	D3	parallel data input
15	CE	clock enable input (active low)
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CP, CE to Q7, Q7	16 (74HC) 14 (74HCT)	ns
Propagation delay, PL to Q7, Q7	15 (74HC) 17 (74HCT)	ns
Propagation delay, D7 to Q7, Q7	11 (74HC) 11 (74HCT)	ns
Maximum clock frequency	56 (74HC) 48 (74HCT)	MHz

Notes

The low-to-high transition of input CE should only take place while CP is high for predictable operation.

Either CP or CE should be high before the low-to-high transition of PL to prevent shifting the data when PL is activated.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74166 - 8-bit parallel-in/serial-out shift register - msarnoff.org ChipDB

74166

8-bit parallel-in/serial-out shift register


D_s	1 •	16	Vcc
D₀	2	15	PE
D₁	3	14	D₇
D₂	4	13	Q₇
D₃	5	12	D₆
CE	6	11	D₅
CP	7	10	D₄
GND	8	9	MR

Pin	Symbol	Description
1	D_s	serial data input
2	D₀	parallel data input
3	D₁	parallel data input
4	D₂	parallel data input
5	D₃	parallel data input
6	CE	clock enable input (active low)
7	CP	clock input (low-to-high, edge-triggered)
8	GND	ground
9	MR	asynchronous master reset (active low)
10	D₄	parallel data input
11	D₅	parallel data input
12	D₆	parallel data input
13	Q₇	serial output from the last stage
14	D₇	parallel data input
15	PE	parallel enable input (active low)
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CP to Q₇	15 (74HC) 20 (74HCT)	ns
Propagation delay, MR to Q₇	14 (74HC) 19 (74HCT)	ns
Maximum clock frequency	63 (74HC) 50 (74HCT)	MHz

Notes

The low-to-high transition of CE should only take place while CP is high for predictable operation.

A low on MR overrides all other inputs and clears the register asynchronously, forcing all bit positions to a low stage.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74173 - Quad D-type flip-flop; positive-edge trigger; 3-state - msarnoff.org ChipDB

74173

Quad D-type flip-flop; positive-edge trigger; 3-state


OE₁	1 •	16	Vcc
OE₂	2	15	MR
Q₀	3	14	D₀
Q₁	4	13	D₁
Q₂	5	12	D₂
Q₃	6	11	D₃
CP	7	10	E₂
GND	8	9	E₁

Pin	Symbol	Description
1	OE₁	output enable input (active low)
2	OE₂	output enable input (active low)
3	Q₀	3-state flip-flop output
4	Q₁	3-state flip-flop output
5	Q₂	3-state flip-flop output
6	Q₃	3-state flip-flop output
7	CP	clock input (low-to-high, edge-triggered)
8	GND	ground
9	E₁	data enable input (active low)
10	E₂	data enable input (active low)
11	D₃	data input
12	D₂	data input
13	D₁	data input
14	D₀	data input
15	MR	asynchronous master reset (active high)
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CP to Q_n	17 (74HC/HCT)	ns
Propagation delay, MR to Q_n	13 (74HC) 17 (74HCT)	ns
Maximum clock frequency	88 (74HC/HCT)	MHz

Notes

When one or both OE_n inputs are high, the outputs are forced to a high-impedance off state.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74174 - Hex D-type flip-flop with reset; positive-edge trigger - msarnoff.org ChipDB

74174

Hex D-type flip-flop with reset; positive-edge trigger


MR	1 •	16	Vcc
Q₀	2	15	Q₅
D₀	3	14	D₅
D₁	4	13	D₄
Q₁	5	12	Q₄
D₂	6	11	D₃
Q₂	7	10	Q₃
GND	8	9	CP

Pin	Symbol	Description
1	MR	asynchronous master reset (active low)
2	Q₀	flip-flop output
3	D₀	data input
4	D₁	data input
5	Q₁	flip-flop output
6	D₂	data input
7	Q₂	flip-flop output
8	GND	ground
9	CP	clock input (low-to-high, edge-triggered)
10	Q₃	flip-flop output
11	D₃	data input
12	Q₄	flip-flop output
13	D₄	data input
14	D₅	data input
15	Q₅	flip-flop output
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CP to Q_n	17 (74HC) 18 (74HCT)	ns
Propagation delay, MR to Q_n	13 (74HC) 17 (74HCT)	ns
Maximum clock frequency	99 (74HC) 69 (74HCT)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74175 - Quad D-type flip-flop with reset; positive-edge trigger - msarnoff.org ChipDB

74175

Quad D-type flip-flop with reset; positive-edge trigger


MR	1 •	16	Vcc
Q₀	2	15	Q₃
Q₀	3	14	Q₃
D₀	4	13	D₃
D₁	5	12	D₂
Q₁	6	11	Q₂
Q₁	7	10	Q₂
GND	8	9	CP

Pin	Symbol	Description
1	MR	asynchronous master reset (active low)
2	Q₀	flip-flop output
3	Q₀	complementary flip-flop output
4	D₀	data input
5	D₁	data input
6	Q₁	complementary flip-flop output
7	Q₁	flip-flop output
8	GND	ground
9	CP	clock input (low-to-high, edge-triggered)
10	Q₂	flip-flop output
11	Q₂	complementary flip-flop output
12	D₂	data input
13	D₃	data input
14	Q₃	complementary flip-flop output
15	Q₃	flip-flop output
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CP to Q_n, Q_n	17 (74HC) 16 (74HCT)	ns
Propagation delay, MR to Q_n	15 (74HC) 19 (74HCT)	ns
Maximum clock frequency	83 (74HC) 54 (74HCT)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74191 - Presettable synchronous 4-bit binary up/down counter - msarnoff.org ChipDB

74191

Presettable synchronous 4-bit binary up/down counter


D₁	1 •	16	Vcc
Q₁	2	15	D₀
Q₀	3	14	CP
CE	4	13	RC
U/D	5	12	TC
Q₂	6	11	PL
Q₃	7	10	D₂
GND	8	9	D₃

Pin	Symbol	Description
1	D₁	data input
2	Q₁	counter output
3	Q₀	counter output
4	CE	count enable input (active low)
5	U/D	up/down input
6	Q₂	counter output
7	Q₃	counter output
8	GND	ground
9	D₃	data input
10	D₂	data input
11	PL	parallel load input (active low)
12	TC	terminal count output
13	RC	ripple clock output (active low)
14	CP	clock input (low-to-high, edge-triggered)
15	D₀	data input
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CP to Q_n	22 (74HC/74HCT)	ns
Maximum clock frequency	36 (74HC/74HCT)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74193 - Presettable synchronous 4-bit binary up/down counter; separate up/down clocks - msarnoff.org ChipDB

74193

Presettable synchronous 4-bit binary up/down counter; separate up/down clocks


D₁	1 •	16	Vcc
Q₁	2	15	D₀
Q₀	3	14	MR
CPD	4	13	TCD
CPU	5	12	TCU
Q₂	6	11	PL
Q₃	7	10	D₂
GND	8	9	D₃

Pin	Symbol	Description
1	D₁	data input
2	Q₁	counter output
3	Q₀	counter output
4	CPD	count down clock input (low-to-high, edge-triggered)
5	CPU	count up clock input (low-to-high, edge-triggered)
6	Q₂	counter output
7	Q₃	counter output
8	GND	ground
9	D₃	data input
10	D₂	data input
11	PL	parallel load input (active low)
12	TCU	terminal count up (carry) output (active low)
13	TCD	terminal count down (borrow) output (active low)
14	MR	asynchronous master reset (active high)
15	D₀	data input
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CPU, CPD to Q_n	23 (74HC) 23 (74HCT)	ns
Propagation delay, CPU to TCU, TCD	14 (74HC) 15 (74HCT)	ns
Propagation delay, PL to Q_n	25 (74HC) 26 (74HCT)	ns
Propagation delay, MR to Q_n	21 (74HC) 22 (74HCT)	ns
Propagation delay, D_n to Q_n	25 (74HC) 27 (74HCT)	ns
Propagation delay, PL to TCU, TCD	29 (74HC) 31 (74HCT)	ns
Propagation delay, MR to TCU, TCD	27 (74HC) 29 (74HCT)	ns
Propagation delay, CPU, D_n to TCU, TCD	29 (74HC) 32 (74HCT)	ns
Maximum frequency	41 (74HC) 43 (74HCT)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74194 - 4-bit bidirectional universal shift register - msarnoff.org ChipDB

74194

4-bit bidirectional universal shift register


MR	1 •	16	Vcc
D_SR	2	15	Q₀
D₀	3	14	Q₁
D₁	4	13	Q₂
D₂	5	12	Q₃
D₃	6	11	CP
D_SL	7	10	S₁
GND	8	9	S₀

Pin	Symbol	Description
1	MR	asynchronous master reset (active low)
2	D_SR	serial data input (shift right)
3	D₀	parallel data input
4	D₁	parallel data input
5	D₂	parallel data input
6	D₃	parallel data input
7	D_SL	serial data input (shift left)
8	GND	ground
9	S₀	mode control input
10	S₁	mode control input
11	CP	clock input (low-to-high, edge-triggered)
12	Q₃	parallel output
13	Q₂	parallel output
14	Q₁	parallel output
15	Q₀	parallel output
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CP to Q_n	14 (74HC) 15 (74HCT)	ns
Propagation delay, MR to Q_n	14 (74HC) 15 (74HCT)	ns
Maximum clock frequency	102 (74HC) 77 (74HCT)	MHz

Notes

S₀ and S₁ are low; hold (do nothing)

S₀ low and S₁ high; shift left

S₀ high and S₁ low; shift right

S₀ and S₁ high; parallel load

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74195 - Universal 4-Bit Shift Register - msarnoff.org ChipDB

74195

Universal 4-Bit Shift Register


MR	1 •	16	VCC
J	2	15	Q₀
K	3	14	Q₁
P₀	4	13	Q₂
P₁	5	12	Q₃
P₂	6	11	Q₃
P₃	7	10	CP
GND	8	9	PE

Pin	Symbol	Description
1	MR	Asynchronous Master Reset (Active Low)
2	J	First Stage J Input (Active High)
3	K	First Stage K Input (Active Low)
4	P₀	Parallel Data Input
5	P₁	Parallel Data Input
6	P₂	Parallel Data Input
7	P₃	Parallel Data Input
8	GND	Ground
9	PE	Parallel Enable Input (Active Low)
10	CP	Clock Pulse Input (Active Rising Edge)
11	Q₃	Complementary Last Stage Output (Active Low)
12	Q₃	Parallel Outputs
13	Q₂	Parallel Outputs
14	Q₁	Parallel Outputs
15	Q₀	Parallel Outputs
16	VCC	Power

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74221 - Dual non-retriggerable monostable multivibrator with reset - msarnoff.org ChipDB

74221

Dual non-retriggerable monostable multivibrator with reset


1A	1 •	16	Vcc
1B	2	15	1REXT/CEXT
1RD	3	14	1CEXT
1Q	4	13	1Q
2Q	5	12	2Q
2CEXT	6	11	2RD
2REXT/CEXT	7	10	2B
GND	8	9	2A

Pin	Symbol	Description
1	1A	negative-edge triggered input 1
2	1B	positive-edge triggered input 1
3	1RD	direct reset (low) and positive-edge triggered input 1
4	1Q	active low output 1
5	2Q	active high output 2
6	2CEXT	external capacitor connection 2
7	2REXT/CEXT	external resistor and capacitor connection 2
8	GND	ground
9	2A	negative-edge triggered input 2
10	2B	positive-edge triggered input 2
11	2RD	direct reset (low) and positive-edge triggered input 2
12	2Q	active low output 2
13	1Q	active high output 1
14	1CEXT	external capacitor connection 1
15	1REXT/CEXT	external resistor and capacitor connection 1
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nRD, nA, nB to nQ or nQ	29 (74HC) 32 (74HCT)	ns
Output transition time	19 (74HC) 7 (74HCT)	ns
External timing resistor	2 (min) 1000 (max)	kΩ

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74237 - 3-to-8 line decoder/demultiplexer with address latches; non-inverting - msarnoff.org ChipDB

74237

3-to-8 line decoder/demultiplexer with address latches; non-inverting


A0	1 •	16	Vcc
A1	2	15	Y0
A2	3	14	Y1
LE	4	13	Y2
E1	5	12	Y3
E2	6	11	Y4
Y7	7	10	Y5
GND	8	9	Y6

Pin	Symbol	Description
1	A0	data input 0
2	A1	data input 1
3	A2	data input 2
4	LE	latch enable input (active low)
5	E1	data enable input 1 (active low)
6	E2	data enable input 2 (active high)
7	Y7	output 7
8	GND	ground
9	Y6	output 6
10	Y5	output 5
11	Y4	output 4
12	Y3	output 3
13	Y2	output 2
14	Y1	output 1
15	Y0	output 0
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, An to Yn	16 (74HC)	ns
Propagation delay, LE to Yn	19 (74HC)	ns
Propagation delay, E1 to Yn	14 (74HC)	ns
Propagation delay, E2 to Yn	14 (74HC)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74238 - 3-to-8 line decoder/demultiplexer; non-inverting - msarnoff.org ChipDB

74238

3-to-8 line decoder/demultiplexer; non-inverting


A0	1 •	16	Vcc
A1	2	15	Y0
A2	3	14	Y1
E1	4	13	Y2
E2	5	12	Y3
E3	6	11	Y4
Y7	7	10	Y5
GND	8	9	Y6

Pin	Symbol	Description
1	A0	data input 0
2	A1	data input 1
3	A2	data input 2
4	E1	enable input 1 (active low)
5	E2	enable input 2 (active low)
6	E3	enable input 3 (active high)
7	Y7	output 7
8	GND	ground
9	Y6	output 6
10	Y5	output 5
11	Y4	output 4
12	Y3	output 3
13	Y2	output 2
14	Y1	output 1
15	Y0	output 0
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, An to Yn	14 (74HC) 18 (74HCT)	ns
Propagation delay, E3 to Yn	16 (74HC) 20 (74HCT)	ns
Propagation delay, En to Yn	17 (74HC) 21 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74240 - Octal buffer/line driver; 3-state; inverting - msarnoff.org ChipDB

74240

Octal buffer/line driver; 3-state; inverting


1OE	1 •	20	Vcc
1A0	2	19	2OE
2Y0	3	18	1Y0
1A1	4	17	2A0
2Y1	5	16	1Y1
1A2	6	15	2A1
2Y2	7	14	1Y2
1A3	8	13	2A2
2Y3	9	12	1Y3
GND	10	11	2A3

Pin	Symbol	Description
1	1OE	output enable (active low)
2	1A0	data input
3	2Y0	bus output
4	1A1	data input
5	2Y1	bus output
6	1A2	data input
7	2Y2	bus output
8	1A3	data input
9	2Y3	bus output
10	GND	ground
11	2A3	data input
12	1Y3	bus output
13	2A2	data input
14	1Y2	bus output
15	2A1	data input
16	1Y1	bus output
17	2A0	data input
18	1Y0	bus output
19	2OE	output enable (active low)
20	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nAn to nYn	9 (74HC/HCT)	ns

Notes

Setting 1OE or 2OE high causes the outputs to assume a high-impedance off state.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74241 - Octal buffer/line driver; 3-state; non-inverting - msarnoff.org ChipDB

74241

Octal buffer/line driver; 3-state; non-inverting


1OE	1 •	20	Vcc
1A0	2	19	2OE
2Y0	3	18	1Y0
1A1	4	17	2A0
2Y1	5	16	1Y1
1A2	6	15	2A1
2Y2	7	14	1Y2
1A3	8	13	2A2
2Y3	9	12	1Y3
GND	10	11	2A3

Pin	Symbol	Description
1	1OE	output enable (active low)
2	1A0	data input
3	2Y0	bus output
4	1A1	data input
5	2Y1	bus output
6	1A2	data input
7	2Y2	bus output
8	1A3	data input
9	2Y3	bus output
10	GND	ground
11	2A3	data input
12	1Y3	bus output
13	2A2	data input
14	1Y2	bus output
15	2A1	data input
16	1Y1	bus output
17	2A0	data input
18	1Y0	bus output
19	2OE	output enable (active high)
20	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nAn to nYn	7 (74HC) 11 (74HCT)	ns

Notes

Setting 1OE high or 2OE low causes the outputs to assume a high-impedance off state.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74243 - Quad bus transceiver; 3-state - msarnoff.org ChipDB

74243

Quad bus transceiver; 3-state


OEA	1 •	14	Vcc
NC	2	13	OEB
A0	3	12	NC
A1	4	11	B0
A2	5	10	B1
A3	6	9	B2
GND	7	8	B3

Pin	Symbol	Description
1	OEA	output enable (active low)
2	NC	no connection
3	A0	data input or output
4	A1	data input or output
5	A2	data input or output
6	A3	data input or output
7	GND	ground
8	B3	data output or input
9	B2	data output or input
10	B1	data output or input
11	B0	data output or input
12	NC	no connection
13	OEB	output enable (active high)
14	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, An to Bn; Bn to An	6 (74HC)	ns

Notes

When OEA and OEB are low, An are inputs.

When OEA and OEB are high, Bn are inputs.

Otherwise, An and Bn are in a high-impedance off state.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74244 - Octal buffer/line driver; 3-state; non-inverting - msarnoff.org ChipDB

74244

Octal buffer/line driver; 3-state; non-inverting


1OE	1 •	20	Vcc
1A0	2	19	2OE
2Y0	3	18	1Y0
1A1	4	17	2A0
2Y1	5	16	1Y1
1A2	6	15	2A1
2Y2	7	14	1Y2
1A3	8	13	2A2
2Y3	9	12	1Y3
GND	10	11	2A3

Pin	Symbol	Description
1	1OE	output enable (active low)
2	1A0	data input
3	2Y0	bus output
4	1A1	data input
5	2Y1	bus output
6	1A2	data input
7	2Y2	bus output
8	1A3	data input
9	2Y3	bus output
10	GND	ground
11	2A3	data input
12	1Y3	bus output
13	2A2	data input
14	1Y2	bus output
15	2A1	data input
16	1Y1	bus output
17	2A0	data input
18	1Y0	bus output
19	2OE	output enable (active low)
20	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nAn to nYn	9 (74HC) 11 (74HCT)	ns

Notes

Setting 1OE or 2OE high causes the outputs to assume a high-impedance off state.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74245 - Octal bus transceiver; 3-state - msarnoff.org ChipDB

74245

Octal bus transceiver; 3-state


DIR	1 •	20	Vcc
A0	2	19	OE
A1	3	18	B0
A2	4	17	B1
A3	5	16	B2
A4	6	15	B3
A5	7	14	B4
A6	8	13	B5
A7	9	12	B6
GND	10	11	B7

Pin	Symbol	Description
1	DIR	direction control
2	A0	data input/output
3	A1	data input/output
4	A2	data input/output
5	A3	data input/output
6	A4	data input/output
7	A5	data input/output
8	A6	data input/output
9	A7	data input/output
10	GND	ground
11	B7	data input/output
12	B6	data input/output
13	B5	data input/output
14	B4	data input/output
15	B3	data input/output
16	B2	data input/output
17	B1	data input/output
18	B0	data input/output
19	OE	output enable (active low)
20	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, An to Bn or Bn to An	7 (74HC) 10 (74HCT)	ns

Notes

When DIR is high, An are inputs.

When DIR is low, Bn are inputs.

When OE is high, An and Bn are in a high-impedance off state.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74251 - 8-input multiplexer; 3-state - msarnoff.org ChipDB

74251

8-input multiplexer; 3-state


I₃	1 •	16	Vcc
I₂	2	15	I₄
I₁	3	14	I₅
I₀	4	13	I₆
Y	5	12	I₇
Y	6	11	S₀
OE	7	10	S₁
GND	8	9	S₂

Pin	Symbol	Description
1	I₃	multiplexer input
2	I₂	multiplexer input
3	I₁	multiplexer input
4	I₀	multiplexer input
5	Y	multiplexer output
6	Y	complementary multiplexer output
7	OE	enable input (active low; outputs in high-impedance off state when high)
8	GND	ground
9	S₂	select input
10	S₁	select input
11	S₀	select input
12	I₇	multiplexer input
13	I₆	multiplexer input
14	I₅	multiplexer input
15	I₄	multiplexer input
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, I_n to Y	15 (74HC) 19 (74HCT)	ns
Propagation delay, I_n to Y	17 (74HC) 19 (74HCT)	ns
Propagation delay, S_n to Y	20 (74HC/HCT)	ns
Propagation delay, S_n to Y	21 (74HC) 21 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74253 - Dual 4-input multiplexer; 3-state - msarnoff.org ChipDB

74253

Dual 4-input multiplexer; 3-state


1OE	1 •	16	Vcc
S₁	2	15	2OE
1I₃	3	14	S₀
1I₂	4	13	2I₃
1I₁	5	12	2I₂
1I₀	6	11	2I₁
1Y	7	10	2I₀
GND	8	9	2Y

Pin	Symbol	Description
1	1OE	enable input 1 (active low)
2	S₁	common data select input
3	1I₃	data input from source 1
4	1I₂	data input from source 1
5	1I₁	data input from source 1
6	1I₀	data input from source 1
7	1Y	multiplexer output from source 1
8	GND	ground
9	2Y	multiplexer output from source 2
10	2I₀	data input from source 2
11	2I₁	data input from source 2
12	2I₂	data input from source 2
13	2I₃	data input from source 2
14	S₀	common data select input
15	2OE	enable input 2 (active low)
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, 1I_n, 2I_n to nY	17 (74HC/HCT)	ns
Propagation delay, S_n to nY	18 (74HC) 19 (74HCT)	ns

Notes

When 1OE or 2OE is high, the outputs are forced to a high-impedance off state.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74257 - Quad 2-input multiplexer; 3-state - msarnoff.org ChipDB

74257

Quad 2-input multiplexer; 3-state


S	1 •	16	Vcc
1I₀	2	15	OE
1I₁	3	14	4I₀
1Y	4	13	4I₁
2I₀	5	12	4Y
2I₁	6	11	3I₀
2Y	7	10	3I₁
GND	8	9	3Y

Pin	Symbol	Description
1	S	common data select input
2	1I₀	data input from source 0
3	1I₁	data input from source 1
4	1Y	multiplexer output
5	2I₀	data input from source 0
6	2I₁	data input from source 1
7	2Y	multiplexer output
8	GND	ground
9	3Y	multiplexer output
10	3I₁	data input from source 1
11	3I₀	data input from source 0
12	4Y	multiplexer output
13	4I₁	data input from source 1
14	4I₀	data input from source 0
15	OE	enable input (active low; outputs in high-impedance off state when high)
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nI₀, nI₁ to nY	11 (74HC) 13 (74HCT)	ns
Propagation delay, S to nY	14 (74HC) 17 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74258 - Quad 2-input multiplexer; 3-state; inverting - msarnoff.org ChipDB

74258

Quad 2-input multiplexer; 3-state; inverting


S	1 •	16	Vcc
1I₀	2	15	OE
1I₁	3	14	4I₀
1Y	4	13	4I₁
2I₀	5	12	4Y
2I₁	6	11	3I₀
2Y	7	10	3I₁
GND	8	9	3Y

Pin	Symbol	Description
1	S	common data select input
2	1I₀	data input from source 0
3	1I₁	data input from source 1
4	1Y	multiplexer output
5	2I₀	data input from source 0
6	2I₁	data input from source 1
7	2Y	multiplexer output
8	GND	ground
9	3Y	multiplexer output
10	3I₁	data input from source 1
11	3I₀	data input from source 0
12	4Y	multiplexer output
13	4I₁	data input from source 1
14	4I₀	data input from source 0
15	OE	enable input (active low; outputs in high-impedance off state when high)
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nI₀, nI₁ to nY	9 (74HC)	ns
Propagation delay, S to nY	14 (74HC)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74259 - 8-bit addressable latch - msarnoff.org ChipDB

74259

8-bit addressable latch


A0	1 •	16	Vcc
A1	2	15	MR
A2	3	14	LE
Q0	4	13	D
Q1	5	12	Q7
Q2	6	11	Q6
Q3	7	10	Q5
GND	8	9	Q4

Pin	Symbol	Description
1	A0	address input
2	A1	address input
3	A2	address input
4	Q0	latch output
5	Q1	latch output
6	Q2	latch output
7	Q3	latch output
8	GND	ground
9	Q4	latch output
10	Q5	latch output
11	Q6	latch output
12	Q7	latch output
13	D	data input
14	LE	latch enable input (active low)
15	MR	conditional reset input (active low)
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, D to Qn	18 (74HC) 20 (74HCT)	ns
Propagation delay, An to Qn	17 (74HC) 20 (74HCT)	ns
Propagation delay, LE to Qn	17 (74HC) 20 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74273 - Octal D-type flip-flop with reset; positive-edge trigger - msarnoff.org ChipDB

74273

Octal D-type flip-flop with reset; positive-edge trigger


MR	1 •	20	Vcc
Q0	2	19	Q7
D0	3	18	D7
D1	4	17	D6
Q1	5	16	Q6
Q2	6	15	Q5
D2	7	14	D5
D3	8	13	D4
Q3	9	12	Q4
GND	10	11	CP

Pin	Symbol	Description
1	MR	master reset input (active low)
2	Q0	flip-flop output
3	D0	data input
4	D1	data input
5	Q1	flip-flop output
6	Q2	flip-flop output
7	D2	data input
8	D3	data input
9	Q3	flip-flop output
10	GND	ground
11	CP	clock input (low-to-high, edge-triggered)
12	Q4	flip-flop output
13	D4	data input
14	D5	data input
15	Q5	flip-flop output
16	Q6	flip-flop output
17	D6	data input
18	D7	data input
19	Q7	flip-flop output
20	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CP to Qn	15 (74HC/HCT)	ns
Maximum clock frequency	66 (74HC) 36 (74HCT)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74280 - 9-bit odd/even parity generator/checker - msarnoff.org ChipDB

74280

9-bit odd/even parity generator/checker


I₆	1 •	14	Vcc
I₇	2	13	I₅
NC	3	12	I₄
I₈	4	11	I₃
Σ_E	5	10	I₂
Σ_O	6	9	I₁
GND	7	8	I₀

Pin	Symbol	Description
1	I₆	data input
2	I₇	data input
3	NC	no connection
4	I₈	data input
5	Σ_E	even parity output
6	Σ_O	odd parity output
7	GND	ground
8	I₀	data input
9	I₁	data input
10	I₂	data input
11	I₃	data input
12	I₄	data input
13	I₅	data input
14	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, I_n to Σ_E	17 (74HC) 18 (74HCT)	ns
Propagation delay, I_n to Σ_O	20 (74HC) 22 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74283 - 4-bit binary full adder with fast carry - msarnoff.org ChipDB

74283

4-bit binary full adder with fast carry


S2	1 •	16	Vcc
B2	2	15	B3
A2	3	14	A3
S1	4	13	S3
A1	5	12	A4
B1	6	11	B4
CIN	7	10	S4
GND	8	9	COUT

Pin	Symbol	Description
1	S2	sum output
2	B2	B operand input
3	A2	A operand input
4	S1	sum output
5	A1	A operand input
6	B1	B operand input
7	CIN	carry input
8	GND	ground
9	COUT	carry output
10	S4	sum output
11	B4	B operand input
12	A4	A operand input
13	S3	sum output
14	A3	A operand input
15	B3	B operand input
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CIN to S1	16 (74HC) 15 (74HCT)	ns
Propagation delay, CIN to S2	18 (74HC) 21 (74HCT)	ns
Propagation delay, CIN to S3	20 (74HC) 23 (74HCT)	ns
Propagation delay, CIN to S4	23 (74HC) 27 (74HCT)	ns
Propagation delay, An, Bn to Sn	21 (74HC) 25 (74HCT)	ns
Propagation delay, CIN to COUT	20 (74HC) 23 (74HCT)	ns
Propagation delay, An, Bn to COUT	20 (74HC) 24 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74299 - 8-bit universal shift register; 3-state - msarnoff.org ChipDB

74299

8-bit universal shift register; 3-state


S0	1 •	20	Vcc
OE1	2	19	S1
OE2	3	18	DSL
I/O6	4	17	Q7
I/O4	5	16	I/O7
I/O2	6	15	I/O5
I/O0	7	14	I/O3
Q0	8	13	I/O1
MR	9	12	CP
GND	10	11	DSR

Pin	Symbol	Description
1	S0	mode select input
2	OE1	output enable (active low)
3	OE2	output enable (active low)
4	I/O6	parallel data input/output
5	I/O4	parallel data input/output
6	I/O2	parallel data input/output
7	I/O0	parallel data input/output
8	Q0	serial output (standard output)
9	MR	asynchronous master reset (active low)
10	GND	ground
11	DSR	serial data shift-right input
12	CP	clock input (low-to-high, edge-triggered)
13	I/O1	parallel data input/output
14	I/O3	parallel data input/output
15	I/O5	parallel data input/output
16	I/O7	parallel data input/output
17	Q7	serial output (standard output)
18	DSL	serial data shift-left input
19	S1	mode select input
20	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CP to Q0, Q7	20 (74HC) 19 (74HCT)	ns
Propagation delay, CP to I/On	20 (74HC) 19 (74HCT)	ns
Propagation delay, MR to Q0, Q7, I/On	20 (74HC) 23 (74HCT)	ns
Maximum clock frequency	50 (74HC) 46 (74HCT)	MHz

Notes

S1 and S0 are low; hold (do nothing)

S1 is high and S0 is low; shift left (DSL → Q7, Q7 → Q6...)

S1 is low and S0 is high; shift right (DSR → Q0, Q0 → Q1...)

S1 and S0 are high; parallel load (I/On → Qn)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74365 - Hex buffer/line driver; 3-state; non-inverting - msarnoff.org ChipDB

74365

Hex buffer/line driver; 3-state; non-inverting


OE₁	1 •	16	Vcc
1A	2	15	OE₂
1Y	3	14	6A
2A	4	13	6Y
2Y	5	12	5A
3A	6	11	5Y
3Y	7	10	4A
GND	8	9	4Y

Pin	Symbol	Description
1	OE₁	output enable (active low)
2	1A	data input
3	1Y	bus output
4	2A	data input
5	2Y	bus output
6	3A	data input
7	3Y	bus output
8	GND	ground
9	4Y	bus output
10	4A	data input
11	5Y	bus output
12	5A	data input
13	6Y	bus output
14	6A	data input
15	OE₂	output enable (active low)
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nA to nY	9 (74HC) 11 (74HCT)	ns

Notes

Setting OE₁ or OE₂ high causes the outputs to assume a high-impedance off state.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74366 - Hex buffer/line driver; 3-state; inverting - msarnoff.org ChipDB

74366

Hex buffer/line driver; 3-state; inverting


OE₁	1 •	16	Vcc
1A	2	15	OE₂
1Y	3	14	6A
2A	4	13	6Y
2Y	5	12	5A
3A	6	11	5Y
3Y	7	10	4A
GND	8	9	4Y

Pin	Symbol	Description
1	OE₁	output enable (active low)
2	1A	data input
3	1Y	bus output
4	2A	data input
5	2Y	bus output
6	3A	data input
7	3Y	bus output
8	GND	ground
9	4Y	bus output
10	4A	data input
11	5Y	bus output
12	5A	data input
13	6Y	bus output
14	6A	data input
15	OE₂	output enable (active low)
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nA to nY	10 (74HC) 11 (74HCT)	ns

Notes

Setting OE₁ or OE₂ high causes the outputs to assume a high-impedance off state.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74367 - Hex buffer/line driver; 3-state; non-inverting - msarnoff.org ChipDB

74367

Hex buffer/line driver; 3-state; non-inverting


OE₁	1 •	16	Vcc
1A	2	15	OE₂
1Y	3	14	6A
2A	4	13	6Y
2Y	5	12	5A
3A	6	11	5Y
3Y	7	10	4A
GND	8	9	4Y

Pin	Symbol	Description
1	OE₁	output enable (active low)
2	1A	data input
3	1Y	bus output
4	2A	data input
5	2Y	bus output
6	3A	data input
7	3Y	bus output
8	GND	ground
9	4Y	bus output
10	4A	data input
11	5Y	bus output
12	5A	data input
13	6Y	bus output
14	6A	data input
15	OE₂	output enable (active low)
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nA to nY	8 (74HC) 11 (74HCT)	ns

Notes

Setting OE₁ or OE₂ high causes the outputs to assume a high-impedance off state.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74368 - Hex buffer/line driver; 3-state; inverting - msarnoff.org ChipDB

74368

Hex buffer/line driver; 3-state; inverting


OE₁	1 •	16	Vcc
1A	2	15	OE₂
1Y	3	14	6A
2A	4	13	6Y
2Y	5	12	5A
3A	6	11	5Y
3Y	7	10	4A
GND	8	9	4Y

Pin	Symbol	Description
1	OE₁	output enable (active low)
2	1A	data input
3	1Y	bus output
4	2A	data input
5	2Y	bus output
6	3A	data input
7	3Y	bus output
8	GND	ground
9	4Y	bus output
10	4A	data input
11	5Y	bus output
12	5A	data input
13	6Y	bus output
14	6A	data input
15	OE₂	output enable (active low)
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nA to nY	9 (74HC) 11 (74HCT)	ns

Notes

Setting OE₁ or OE₂ high causes the outputs to assume a high-impedance off state.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74373 - Octal D-type transparent latch; 3-state - msarnoff.org ChipDB

74373

Octal D-type transparent latch; 3-state


OE	1 •	20	Vcc
Q0	2	19	Q7
D0	3	18	D7
D1	4	17	D6
Q1	5	16	Q6
Q2	6	15	Q5
D2	7	14	D5
D3	8	13	D4
Q3	9	12	Q4
GND	10	11	LE

Pin	Symbol	Description
1	OE	output enable (active low)
2	Q0	latch output
3	D0	data input
4	D1	data input
5	Q1	latch output
6	Q2	latch output
7	D2	data input
8	D3	data input
9	Q3	latch output
10	GND	ground
11	LE	latch enable (active high)
12	Q4	latch output
13	D4	data input
14	D5	data input
15	Q5	latch output
16	Q6	latch output
17	D6	data input
18	D7	data input
19	Q7	latch output
20	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, Dn to Qn	12 (74HC) 14 (74HCT)	ns
Propagation delay, LE to Qn	15 (74HC) 13 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74374 - Octal D-type flip-flop; positive-edge trigger; 3-state - msarnoff.org ChipDB

74374

Octal D-type flip-flop; positive-edge trigger; 3-state


OE	1 •	20	Vcc
Q0	2	19	Q7
D0	3	18	D7
D1	4	17	D6
Q1	5	16	Q6
Q2	6	15	Q5
D2	7	14	D5
D3	8	13	D4
Q3	9	12	Q4
GND	10	11	CP

Pin	Symbol	Description
1	OE	output enable (active low)
2	Q0	flip-flop output
3	D0	data input
4	D1	data input
5	Q1	flip-flop output
6	Q2	flip-flop output
7	D2	data input
8	D3	data input
9	Q3	flip-flop output
10	GND	ground
11	CP	clock input (low-to-high, edge-triggered)
12	Q4	flip-flop output
13	D4	data input
14	D5	data input
15	Q5	flip-flop output
16	Q6	flip-flop output
17	D6	data input
18	D7	data input
19	Q7	flip-flop output
20	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CP to Qn	15 (74HC) 13 (74HCT)	ns
Maximum clock frequency	77 (74HC) 48 (74HCT)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74377 - Octal D-type flip-flop with data enable; positive-edge trigger - msarnoff.org ChipDB

74377

Octal D-type flip-flop with data enable; positive-edge trigger


E	1 •	20	Vcc
Q0	2	19	Q7
D0	3	18	D7
D1	4	17	D6
Q1	5	16	Q6
Q2	6	15	Q5
D2	7	14	D5
D3	8	13	D4
Q3	9	12	Q4
GND	10	11	CP

Pin	Symbol	Description
1	E	data enable (active low)
2	Q0	flip-flop output
3	D0	data input
4	D1	data input
5	Q1	flip-flop output
6	Q2	flip-flop output
7	D2	data input
8	D3	data input
9	Q3	flip-flop output
10	GND	ground
11	CP	clock input (low-to-high, edge-triggered)
12	Q4	flip-flop output
13	D4	data input
14	D5	data input
15	Q5	flip-flop output
16	Q6	flip-flop output
17	D6	data input
18	D7	data input
19	Q7	flip-flop output
20	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CP to Qn	13 (74HC) 14 (74HCT)	ns
Maximum clock frequency	77 (74HC) 53 (74HCT)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74390 - Dual decade ripple counter - msarnoff.org ChipDB

74390

Dual decade ripple counter


1CP₀	1 •	16	Vcc
1MR	2	15	2CP₀
1Q₀	3	14	2MR
1CP₁	4	13	2Q₀
1Q₁	5	12	2CP₁
1Q₂	6	11	2Q₁
1Q₃	7	10	2Q₂
GND	8	9	2Q₃

Pin	Symbol	Description
1	1CP₀	clock input, divide-by-2 section (high-to-low, edge-triggered)
2	1MR	asynchronous master reset (active high)
3	1Q₀	flip-flop output
4	1CP₁	clock input, divide-by-5 section (high-to-low, edge-triggered)
5	1Q₁	flip-flop output
6	1Q₂	flip-flop output
7	1Q₃	flip-flop output
8	GND	ground
9	2Q₃	flip-flop output
10	2Q₂	flip-flop output
11	2Q₁	flip-flop output
12	2CP₁	clock input, divide-by-5 section (high-to-low, edge-triggered)
13	2Q₀	flip-flop output
14	2MR	asynchronous master reset (active high)
15	2CP₀	clock input, divide-by-2 section (high-to-low, edge-triggered)
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nCP₀ to nQ₀	14 (74HC) 18 (74HCT)	ns
Propagation delay, nCP₁ to nQ₁	15 (74HC) 19 (74HCT)	ns
Propagation delay, nCP₁ to nQ₂	23 (74HC) 26 (74HCT)	ns
Propagation delay, nCP₁ to nQ₃	15 (74HC) 19 (74HCT)	ns
Propagation delay, nMR to nQ_n	16 (74HC) 18 (74HCT)	ns
Maximum clock frequency, nCP₀ and nCP₁	66 (74HC) 61 (74HCT)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74393 - Dual 4-bit binary ripple counter - msarnoff.org ChipDB

74393

Dual 4-bit binary ripple counter


1CP	1 •	14	Vcc
1MR	2	13	2CP
1Q0	3	12	2MR
1Q1	4	11	2Q0
1Q2	5	10	2Q1
1Q3	6	9	2Q2
GND	7	8	2Q3

Pin	Symbol	Description
1	1CP	clock input (high-to-low, edge-triggered)
2	1MR	asynchronous master reset (active high)
3	1Q0	flip-flop output
4	1Q1	flip-flop output
5	1Q2	flip-flop output
6	1Q3	flip-flop output
7	GND	ground
8	2Q3	flip-flop output
9	2Q2	flip-flop output
10	2Q1	flip-flop output
11	2Q0	flip-flop output
12	2MR	asynchronous master reset (active high)
13	2CP	clock input (high-to-low, edge-triggered)
14	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nCP to nQ0	12 (74HC) 20 (74HCT)	ns
Propagation delay, nQx to nQ(x+1)	5 (74HC) 6 (74HCT)	ns
Propagation delay, nMR to nQx	11 (74HC) 15 (74HCT)	ns
Maximum clock frequency	99 (74HC) 53 (74HCT)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74423 - Dual retriggerable monostable multivibrator with reset - msarnoff.org ChipDB

74423

Dual retriggerable monostable multivibrator with reset


1A	1 •	16	Vcc
1B	2	15	1REXT/CEXT
1RD	3	14	1CEXT
1Q	4	13	1Q
2Q	5	12	2Q
2CEXT	6	11	2RD
2REXT/CEXT	7	10	2B
GND	8	9	2A

Pin	Symbol	Description
1	1A	negative-edge triggered input 1
2	1B	positive-edge triggered input 1
3	1RD	direct reset (active low) 1
4	1Q	active low output 1
5	2Q	active high output 2
6	2CEXT	external capacitor connection 2
7	2REXT/CEXT	external resistor and capacitor connection 2
8	GND	ground
9	2A	negative-edge triggered input 2
10	2B	positive-edge triggered input 2
11	2RD	direct reset (active low) 2
12	2Q	active low output 2
13	1Q	active high output 1
14	1CEXT	external capacitor connection 1
15	1REXT/CEXT	external resistor and capacitor connection 1
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nRD, nA, nB to nQ or nQ	25 (74HC) 26(74HCT)	ns
Propagation delay, nRD to nQ or nQ	20 (74HC) 22 (74HCT)	ns
Output transition time	7 (74HC/HCT)	ns
Retrigger time nA, nB	110 (74HC/HCT)	ns
External timing resistor	2 (min) 1000 (max)	kΩ

Notes

The 74423 is identical to the 74123, except it cannot be triggered via the reset input.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74540 - Octal buffer/line driver; 3-state; inverting - msarnoff.org ChipDB

74540

Octal buffer/line driver; 3-state; inverting


OE1	1 •	20	Vcc
A₀	2	19	OE₂
A₁	3	18	Y₀
A₂	4	17	Y₁
A₃	5	16	Y₂
A₄	6	15	Y₃
A₅	7	14	Y₄
A₆	8	13	Y₅
A₇	9	12	Y₆
GND	10	11	Y₇

Pin	Symbol	Description
1	OE1	output enable (active low)
2	A₀	data input
3	A₁	data input
4	A₂	data input
5	A₃	data input
6	A₄	data input
7	A₅	data input
8	A₆	data input
9	A₇	data input
10	GND	ground
11	Y₇	bus output
12	Y₆	bus output
13	Y₅	bus output
14	Y₄	bus output
15	Y₃	bus output
16	Y₂	bus output
17	Y₁	bus output
18	Y₀	bus output
19	OE₂	output enable (active low)
20	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, A_n to Y_n	9 (74HC) 11 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74541 - Octal buffer/line driver; 3-state; non-inverting - msarnoff.org ChipDB

74541

Octal buffer/line driver; 3-state; non-inverting


OE1	1 •	20	Vcc
A₀	2	19	OE₂
A₁	3	18	Y₀
A₂	4	17	Y₁
A₃	5	16	Y₂
A₄	6	15	Y₃
A₅	7	14	Y₄
A₆	8	13	Y₅
A₇	9	12	Y₆
GND	10	11	Y₇

Pin	Symbol	Description
1	OE1	output enable (active low)
2	A₀	data input
3	A₁	data input
4	A₂	data input
5	A₃	data input
6	A₄	data input
7	A₅	data input
8	A₆	data input
9	A₇	data input
10	GND	ground
11	Y₇	bus output
12	Y₆	bus output
13	Y₅	bus output
14	Y₄	bus output
15	Y₃	bus output
16	Y₂	bus output
17	Y₁	bus output
18	Y₀	bus output
19	OE₂	output enable (active low)
20	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, A_n to Y_n	10 (74HC) 12 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74563 - Octal D-type transparent latch; 3-state; inverting - msarnoff.org ChipDB

74563

Octal D-type transparent latch; 3-state; inverting


OE	1 •	20	Vcc
D₀	2	19	Q₀
D₁	3	18	Q₁
D₂	4	17	Q₂
D₃	5	16	Q₃
D₄	6	15	Q₄
D₅	7	14	Q₅
D₆	8	13	Q₆
D₇	9	12	Q₇
GND	10	11	LE

Pin	Symbol	Description
1	OE	output enable (active low)
2	D₀	data input
3	D₁	data input
4	D₂	data input
5	D₃	data input
6	D₄	data input
7	D₅	data input
8	D₆	data input
9	D₇	data input
10	GND	ground
11	LE	latch enable (active high)
12	Q₇	latch output
13	Q₆	latch output
14	Q₅	latch output
15	Q₄	latch output
16	Q₃	latch output
17	Q₂	latch output
18	Q₁	latch output
19	Q₀	latch output
20	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, D_n, LE to Q_n	14 (74HC) 16 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74564 - Octal D-type flip-flop; positive-edge trigger; 3-state; inverting - msarnoff.org ChipDB

74564

Octal D-type flip-flop; positive-edge trigger; 3-state; inverting


OE	1 •	20	Vcc
D₀	2	19	Q₀
D₁	3	18	Q₁
D₂	4	17	Q₂
D₃	5	16	Q₃
D₄	6	15	Q₄
D₅	7	14	Q₅
D₆	8	13	Q₆
D₇	9	12	Q₇
GND	10	11	CP

Pin	Symbol	Description
1	OE	output enable (active low)
2	D₀	data input
3	D₁	data input
4	D₂	data input
5	D₃	data input
6	D₄	data input
7	D₅	data input
8	D₆	data input
9	D₇	data input
10	GND	ground
11	CP	clock input (low-to-high, edge-triggered)
12	Q₇	flip-flop output
13	Q₆	flip-flop output
14	Q₅	flip-flop output
15	Q₄	flip-flop output
16	Q₃	flip-flop output
17	Q₂	flip-flop output
18	Q₁	flip-flop output
19	Q₀	flip-flop output
20	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CP to Q_n	15 (74HC)	ns
Maximum clock frequency	127 (74HC)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74573 - Octal D-type transparent latch; 3-state; non-inverting - msarnoff.org ChipDB

74573

Octal D-type transparent latch; 3-state; non-inverting


OE	1 •	20	Vcc
D₀	2	19	Q₀
D₁	3	18	Q₁
D₂	4	17	Q₂
D₃	5	16	Q₃
D₄	6	15	Q₄
D₅	7	14	Q₅
D₆	8	13	Q₆
D₇	9	12	Q₇
GND	10	11	LE

Pin	Symbol	Description
1	OE	output enable (active low)
2	D₀	data input
3	D₁	data input
4	D₂	data input
5	D₃	data input
6	D₄	data input
7	D₅	data input
8	D₆	data input
9	D₇	data input
10	GND	ground
11	LE	latch enable (active high)
12	Q₇	latch output
13	Q₆	latch output
14	Q₅	latch output
15	Q₄	latch output
16	Q₃	latch output
17	Q₂	latch output
18	Q₁	latch output
19	Q₀	latch output
20	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, D_n to Q_n	14 (74HC) 17 (74HCT)	ns
Propagation delay, LE to Q_n	15 (74HC/HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74574 - Octal D-type flip-flop; positive-edge trigger; 3-state; non-inverting - msarnoff.org ChipDB

74574

Octal D-type flip-flop; positive-edge trigger; 3-state; non-inverting


OE	1 •	20	Vcc
D₀	2	19	Q₀
D₁	3	18	Q₁
D₂	4	17	Q₂
D₃	5	16	Q₃
D₄	6	15	Q₄
D₅	7	14	Q₅
D₆	8	13	Q₆
D₇	9	12	Q₇
GND	10	11	CP

Pin	Symbol	Description
1	OE	output enable (active low)
2	D₀	data input
3	D₁	data input
4	D₂	data input
5	D₃	data input
6	D₄	data input
7	D₅	data input
8	D₆	data input
9	D₇	data input
10	GND	ground
11	CP	clock input (low-to-high, edge-triggered)
12	Q₇	flip-flop output
13	Q₆	flip-flop output
14	Q₅	flip-flop output
15	Q₄	flip-flop output
16	Q₃	flip-flop output
17	Q₂	flip-flop output
18	Q₁	flip-flop output
19	Q₀	flip-flop output
20	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CP to Q_n	14 (74HC) 15 (74HCT)	ns
Maximum clock frequency	123 (74HC) 76 (74HCT)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74590 - 8-bit binary counter with output register; 3-state - msarnoff.org ChipDB

74590

8-bit binary counter with output register; 3-state


Q1	1 •	16	Vcc
Q2	2	15	Q0
Q3	3	14	OE
Q4	4	13	CPR
Q5	5	12	CE
Q6	6	11	CPC
Q7	7	10	MRC
GND	8	9	RCO

Pin	Symbol	Description
1	Q1	parallel data output
2	Q2	parallel data output
3	Q3	parallel data output
4	Q4	parallel data output
5	Q5	parallel data output
6	Q6	parallel data output
7	Q7	parallel data output
8	GND	ground
9	RCO	ripple carry output (active low)
10	MRC	master reset (active low)
11	CPC	counter clock input (active high)
12	CE	count enable (active low)
13	CPR	register clock input (active high)
14	OE	output enable (active low)
15	Q0	parallel data output
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CPR to RCO	19 (74HC)	ns
Propagation delay, CPR to Qn	18 (74HC)	ns
Maximum frequency, CPC and CPR	52 (74HC)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74594 - 8-bit shift register with output register - msarnoff.org ChipDB

74594

8-bit shift register with output register


Q1	1 •	16	Vcc
Q2	2	15	Q0
Q3	3	14	DS
Q4	4	13	STR
Q5	5	12	STCP
Q6	6	11	SHCP
Q7	7	10	SHR
GND	8	9	Q7S

Pin	Symbol	Description
1	Q1	parallel data output
2	Q2	parallel data output
3	Q3	parallel data output
4	Q4	parallel data output
5	Q5	parallel data output
6	Q6	parallel data output
7	Q7	parallel data output
8	GND	ground
9	Q7S	serial data output
10	SHR	shift register reset (active low)
11	SHCP	shift register clock input
12	STCP	storage register clock input
13	STR	storage register reset (active low)
14	DS	serial data input
15	Q0	parallel data output
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, SHCP to Q7S	13 (74HC) 15 (74HCT)	ns
Propagation delay, STCP to Qn	13 (74HC) 15 (74HCT)	ns
Maximum frequency, SHCP or STCP	100 (74HC/74HCT)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74595 - 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state - msarnoff.org ChipDB

74595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state


Q1	1 •	16	Vcc
Q2	2	15	Q0
Q3	3	14	DS
Q4	4	13	OE
Q5	5	12	RCK
Q6	6	11	SCK
Q7	7	10	MR
GND	8	9	Q7'

Pin	Symbol	Description
1	Q1	parallel data output
2	Q2	parallel data output
3	Q3	parallel data output
4	Q4	parallel data output
5	Q5	parallel data output
6	Q6	parallel data output
7	Q7	parallel data output
8	GND	ground
9	Q7'	serial data output
10	MR	master reset (active low)
11	SCK	shift register clock input
12	RCK	storage register latch input
13	OE	output enable (active low)
14	DS	serial data input
15	Q0	parallel data output
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, SCK to Q7'	19 (74HC) 25 (74HCT)	ns
Propagation delay, SCK to Qn	20 (74HC) 24 (74HCT)	ns
Propagation delay, MR to Q7'	100 (74HC) 52 (74HCT)	ns
Maximum clock frequency, SCK and RCK	100 (74HC) 57 (74HCT)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74597 - 8-bit shift register with input flip-flops - msarnoff.org ChipDB

74597

8-bit shift register with input flip-flops


D₁	1 •	16	Vcc
D₂	2	15	D₀
D₃	3	14	D_S
D₄	4	13	PL
D₅	5	12	ST_CP
D₆	6	11	SH_CP
D₇	7	10	MR
GND	8	9	Q

Pin	Symbol	Description
1	D₁	parallel data input
2	D₂	parallel data input
3	D₃	parallel data input
4	D₄	parallel data input
5	D₅	parallel data input
6	D₆	parallel data input
7	D₇	parallel data input
8	GND	ground
9	Q	serial data output
10	MR	asynchronous master reset (active low)
11	SH_CP	shift clock input (low-to-high, edge-triggered)
12	ST_CP	storage clock input (low-to-high, edge-triggered)
13	PL	parallel load input (active low)
14	D_S	serial data input
15	D₀	parallel data input
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, SH_CP to Q	17 (74HC) 20 (74HCT)	ns
Propagation delay, ST_CP to Q	25 (74HC) 29 (74HCT)	ns
Propagation delay, PL to Q	21 (74HC) 26 (74HCT)	ns
Maximum clock frequency, SH_CP	96 (74HC) 83 (74HCT)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74640 - Octal bus transceiver; 3-state; inverting - msarnoff.org ChipDB

74640

Octal bus transceiver; 3-state; inverting


DIR	1 •	20	Vcc
A₀	2	19	OE
A₁	3	18	B₀
A₂	4	17	B₁
A₃	5	16	B₂
A₄	6	15	B₃
A₅	7	14	B₄
A₆	8	13	B₅
A₇	9	12	B₆
GND	10	11	B₇

Pin	Symbol	Description
1	DIR	direction control
2	A₀	data input/output
3	A₁	data input/output
4	A₂	data input/output
5	A₃	data input/output
6	A₄	data input/output
7	A₅	data input/output
8	A₆	data input/output
9	A₇	data input/output
10	GND	ground
11	B₇	data input/output
12	B₆	data input/output
13	B₅	data input/output
14	B₄	data input/output
15	B₃	data input/output
16	B₂	data input/output
17	B₁	data input/output
18	B₀	data input/output
19	OE	output enable (active low)
20	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, A_n to B_n	11 (74HC/HCT)	ns
Propagation delay, B_n to A_n	9 (74HC) 11 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74646 - Octal bus transceiver/register; 3-state - msarnoff.org ChipDB

74646

Octal bus transceiver/register; 3-state


CP_AB	1 •	24	Vcc
S_AB	2	23	CP_BA
DIR	3	22	S_BA
A₀	4	21	OE
A₁	5	20	B₀
A₂	6	19	B₁
A₃	7	18	B₂
A₄	8	17	B₃
A₅	9	16	B₄
A₆	10	15	B₅
A₇	11	14	B₆
GND	12	13	B₇

Pin	Symbol	Description
1	CP_AB	A to B clock input (low-to-high, edge-triggered)
2	S_AB	select A to B source input
3	DIR	direction control input
4	A₀	A data input/output
5	A₁	A data input/output
6	A₂	A data input/output
7	A₃	A data input/output
8	A₄	A data input/output
9	A₅	A data input/output
10	A₆	A data input/output
11	A₇	A data input/output
12	GND	ground
13	B₇	B data input/output
14	B₆	B data input/output
15	B₅	B data input/output
16	B₄	B data input/output
17	B₃	B data input/output
18	B₂	B data input/output
19	B₁	B data input/output
20	B₀	B data input/output
21	OE	output enable (active low)
22	S_BA	select B to A source input
23	CP_BA	B to A clock input (low-to-high, edge-triggered)
24	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, A_n, B_n to B_n, A_n	11 (74HC) 13 (74HCT)	ns
Maximum clock frequency	69 (74HC) 85 (74HCT)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74652 - Octal bus transceiver/register; 3-state - msarnoff.org ChipDB

74652

Octal bus transceiver/register; 3-state


CP_AB	1 •	24	Vcc
S_AB	2	23	CP_BA
OE_AB	3	22	S_BA
A₀	4	21	OE_BA
A₁	5	20	B₀
A₂	6	19	B₁
A₃	7	18	B₂
A₄	8	17	B₃
A₅	9	16	B₄
A₆	10	15	B₅
A₇	11	14	B₆
GND	12	13	B₇

Pin	Symbol	Description
1	CP_AB	A to B clock input (low-to-high, edge-triggered)
2	S_AB	select A to B source input
3	OE_AB	output enable A to B
4	A₀	A data input/output
5	A₁	A data input/output
6	A₂	A data input/output
7	A₃	A data input/output
8	A₄	A data input/output
9	A₅	A data input/output
10	A₆	A data input/output
11	A₇	A data input/output
12	GND	ground
13	B₇	B data input/output
14	B₆	B data input/output
15	B₅	B data input/output
16	B₄	B data input/output
17	B₃	B data input/output
18	B₂	B data input/output
19	B₁	B data input/output
20	B₀	B data input/output
21	OE_BA	output enable B to A (active low)
22	S_BA	select B to A source input
23	CP_BA	B to A clock input (low-to-high, edge-triggered)
24	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, A_n/B_n to B_n/A_n	13 (74HC/HCT)	ns
Propagation delay, CP_AB/CP_BA to B_n/A_n	18 (74HC) 20 (74HCT)	ns
Propagation delay, S_AB/S_BA to B_n/A_n	20 (74HC) 23 (74HCT)	ns
Maximum clock frequency	92 (74HC/HCT)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74670 - 4 by 4 register file; 3-state - msarnoff.org ChipDB

74670

4 by 4 register file; 3-state


D₁	1 •	16	Vcc
D₂	2	15	D₀
D₃	3	14	W_A
R_B	4	13	W_B
R_A	5	12	WE
Q₃	6	11	RE
Q₂	7	10	Q₀
GND	8	9	Q₁

Pin	Symbol	Description
1	D₁	data input
2	D₂	data input
3	D₃	data input
4	R_B	read address input
5	R_A	read address input
6	Q₃	data output
7	Q₂	data output
8	GND	ground
9	Q₁	data output
10	Q₀	data output
11	RE	3-state output read enable (active low)
12	WE	write enable (active low)
13	W_B	write address input
14	W_A	write address input
15	D₀	data input
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, D_n to Q_n	23 (74HC/HCT]	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74688 - 8-bit magnitude comparator - msarnoff.org ChipDB

74688

8-bit magnitude comparator


E	1 •	20	Vcc
P₀	2	19	P=Q
Q₀	3	18	Q₇
P₁	4	17	P₇
Q₁	5	16	Q₆
P₂	6	15	P₆
Q₂	7	14	Q₅
P₃	8	13	P₅
Q₃	9	12	Q₄
GND	10	11	P₄

Pin	Symbol	Description
1	E	enable (active low)
2	P₀	word input
3	Q₀	word input
4	P₁	word input
5	Q₁	word input
6	P₂	word input
7	Q₂	word input
8	P₃	word input
9	Q₃	word input
10	GND	ground
11	P₄	word input
12	Q₄	word input
13	P₅	word input
14	Q₅	word input
15	P₆	word input
16	Q₆	word input
17	P₇	word input
18	Q₇	word input
19	P=Q	equal-to output (low when P = Q)
20	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, P_n, Q_n to P=Q	17 (74HC/HCT)	ns
Propagation delay, E to P=Q	8 (74HC) 12 (74HCT)	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

8254 - Programmable interval timer - msarnoff.org ChipDB

8254

Programmable interval timer


D7	1 •	24	Vcc
D6	2	23	WR
D5	3	22	RD
D4	4	21	CS
D3	5	20	A1
D2	6	19	A0
D1	7	18	CLK 2
D0	8	17	OUT 2
CLK 0	9	16	GATE 2
OUT 0	10	15	CLK 1
GATE 0	11	14	GATE 1
GND	12	13	OUT 1

Pin	Symbol	Description
1	D7	data bus
2	D6	data bus
3	D5	data bus
4	D4	data bus
5	D3	data bus
6	D2	data bus
7	D1	data bus
8	D0	data bus
9	CLK 0	counter 0 clock input
10	OUT 0	counter 0 output
11	GATE 0	counter 0 gate input
12	GND	ground
13	OUT 1	counter 1 output
14	GATE 1	counter 1 gate input
15	CLK 1	counter 1 clock input
16	GATE 2	counter 2 gate input
17	OUT 2	counter 2 output
18	CLK 2	counter 2 clock input
19	A0	address bus
20	A1	address bus
21	CS	chip select (active low)
22	RD	read enable (active low)
23	WR	write enable (active low)
24	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum clock input frequency	8 (8254) 10 (8254-2)	MHz

Notes

Control word:

Bit 0	0=binary (16 bits), 1=BCD (4 decades)
Bits 1-3	mode select
Bits 4-5	read/write mode
Bits 6-7	select counter/read-back mode

Mode 0: interrupt on terminal count

Mode 1: hardware retriggerable one-shot

Mode 2: rate generator

Mode 3: square wave

Mode 4: software triggered strobe

Mode 5: hardware triggered strobe (retriggerable)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

8255A - Programmable peripheral interface - msarnoff.org ChipDB

8255A

Programmable peripheral interface


PA3	1 •	40	PA4
PA2	2	39	PA5
PA1	3	38	PA6
PA0	4	37	PA7
RD	5	36	WR
CS	6	35	RESET
GND	7	34	D0
A1	8	33	D1
A0	9	32	D2
PC7	10	31	D3
PC6	11	30	D4
PC5	12	29	D5
PC4	13	28	D6
PC0	14	27	D7
PC1	15	26	Vcc
PC2	16	25	PB7
PC3	17	24	PB6
PB0	18	23	PB5
PB1	19	22	PB4
PB2	20	21	PB3

Pin	Symbol	Description
1	PA3	port A
2	PA2	port A
3	PA1	port A
4	PA0	port A
5	RD	read enable (active low)
6	CS	chip select (active low)
7	GND	ground
8	A1	address input
9	A0	address input
10	PC7	port C
11	PC6	port C
12	PC5	port C
13	PC4	port C
14	PC0	port C
15	PC1	port C
16	PC2	port C
17	PC3	port C
18	PB0	port B
19	PB1	port B
20	PB2	port B
21	PB3	port B
22	PB4	port B
23	PB5	port B
24	PB6	port B
25	PB7	port B
26	Vcc	supply voltage
27	D7	data bus
28	D6	data bus
29	D5	data bus
30	D4	data bus
31	D3	data bus
32	D2	data bus
33	D1	data bus
34	D0	data bus
35	RESET	reset (active high)
36	WR	write enable (active low)
37	PA7	port A
38	PA6	port A
39	PA5	port A
40	PA4	port A

Notes

Control word:

Bit 0	Port C lower bits; 1=input, 0=output
Bit 1	Port B; 1=input, 0=output
Bit 2	Group B mode selection
Bit 3	Port C upper bits; 1=input, 0=output
Bit 4	Port A; 1=input, 0=output
Bits 5-6	Group A mode selection
Bit 7	1=mode set, 0=bit set/reset

When bit 7 of control word is set to 1, the rest of the bits have the following functions:

Bit 0	1=set bit, 0=clear bit
Bits 1-3	specify bit to modify (0-7)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

8254 - Programmable interval timer - msarnoff.org ChipDB

8254

Programmable interval timer


D7	1 •	24	Vcc
D6	2	23	WR
D5	3	22	RD
D4	4	21	CS
D3	5	20	A1
D2	6	19	A0
D1	7	18	CLK 2
D0	8	17	OUT 2
CLK 0	9	16	GATE 2
OUT 0	10	15	CLK 1
GATE 0	11	14	GATE 1
GND	12	13	OUT 1

Pin	Symbol	Description
1	D7	data bus
2	D6	data bus
3	D5	data bus
4	D4	data bus
5	D3	data bus
6	D2	data bus
7	D1	data bus
8	D0	data bus
9	CLK 0	counter 0 clock input
10	OUT 0	counter 0 output
11	GATE 0	counter 0 gate input
12	GND	ground
13	OUT 1	counter 1 output
14	GATE 1	counter 1 gate input
15	CLK 1	counter 1 clock input
16	GATE 2	counter 2 gate input
17	OUT 2	counter 2 output
18	CLK 2	counter 2 clock input
19	A0	address bus
20	A1	address bus
21	CS	chip select (active low)
22	RD	read enable (active low)
23	WR	write enable (active low)
24	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum clock input frequency	8 (8254) 10 (8254-2)	MHz

Notes

Control word:

Bit 0	0=binary (16 bits), 1=BCD (4 decades)
Bits 1-3	mode select
Bits 4-5	read/write mode
Bits 6-7	select counter/read-back mode

Mode 0: interrupt on terminal count

Mode 1: hardware retriggerable one-shot

Mode 2: rate generator

Mode 3: square wave

Mode 4: software triggered strobe

Mode 5: hardware triggered strobe (retriggerable)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

8255A - Programmable peripheral interface - msarnoff.org ChipDB

8255A

Programmable peripheral interface


PA3	1 •	40	PA4
PA2	2	39	PA5
PA1	3	38	PA6
PA0	4	37	PA7
RD	5	36	WR
CS	6	35	RESET
GND	7	34	D0
A1	8	33	D1
A0	9	32	D2
PC7	10	31	D3
PC6	11	30	D4
PC5	12	29	D5
PC4	13	28	D6
PC0	14	27	D7
PC1	15	26	Vcc
PC2	16	25	PB7
PC3	17	24	PB6
PB0	18	23	PB5
PB1	19	22	PB4
PB2	20	21	PB3

Pin	Symbol	Description
1	PA3	port A
2	PA2	port A
3	PA1	port A
4	PA0	port A
5	RD	read enable (active low)
6	CS	chip select (active low)
7	GND	ground
8	A1	address input
9	A0	address input
10	PC7	port C
11	PC6	port C
12	PC5	port C
13	PC4	port C
14	PC0	port C
15	PC1	port C
16	PC2	port C
17	PC3	port C
18	PB0	port B
19	PB1	port B
20	PB2	port B
21	PB3	port B
22	PB4	port B
23	PB5	port B
24	PB6	port B
25	PB7	port B
26	Vcc	supply voltage
27	D7	data bus
28	D6	data bus
29	D5	data bus
30	D4	data bus
31	D3	data bus
32	D2	data bus
33	D1	data bus
34	D0	data bus
35	RESET	reset (active high)
36	WR	write enable (active low)
37	PA7	port A
38	PA6	port A
39	PA5	port A
40	PA4	port A

Notes

Control word:

Bit 0	Port C lower bits; 1=input, 0=output
Bit 1	Port B; 1=input, 0=output
Bit 2	Group B mode selection
Bit 3	Port C upper bits; 1=input, 0=output
Bit 4	Port A; 1=input, 0=output
Bits 5-6	Group A mode selection
Bit 7	1=mode set, 0=bit set/reset

When bit 7 of control word is set to 1, the rest of the bits have the following functions:

Bit 0	1=set bit, 0=clear bit
Bits 1-3	specify bit to modify (0-7)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

A6278 - Serial-input constant-current latched LED driver (8 outputs) - msarnoff.org ChipDB

A6278

Serial-input constant-current latched LED driver (8 outputs)


GND	1 •	16	Vcc
DATA	2	15	REXT
CLOCK	3	14	DATA OUT
LATCH	4	13	OE
OUT0	5	12	OUT7
OUT1	6	11	OUT6
OUT2	7	10	OUT5
OUT3	8	9	OUT4

Pin	Symbol	Description
1	GND	ground
2	DATA	serial data in
3	CLOCK	clock input (low-to-high triggered)
4	LATCH	data strobe input (active high)
5	OUT0	current-sinking output
6	OUT1	current-sinking output
7	OUT2	current-sinking output
8	OUT3	current-sinking output
9	OUT4	current-sinking output
10	OUT5	current-sinking output
11	OUT6	current-sinking output
12	OUT7	current-sinking output
13	OE	output enable (active low)
14	DATA OUT	serial data out, for cascading
15	REXT	external resistor to ground (sets output current)
16	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

A6279 - Serial-input constant-current latched LED driver (16 outputs) - msarnoff.org ChipDB

A6279

Serial-input constant-current latched LED driver (16 outputs)


GND	1 •	24	Vcc
DATA	2	23	REXT
CLOCK	3	22	DATA OUT
LATCH	4	21	OE
OUT0	5	20	OUT15
OUT1	6	19	OUT14
OUT2	7	18	OUT13
OUT3	8	17	OUT12
OUT4	9	16	OUT11
OUT5	10	15	OUT10
OUT6	11	14	OUT9
OUT7	12	13	OUT8

Pin	Symbol	Description
1	GND	ground
2	DATA	serial data in
3	CLOCK	clock input (low-to-high triggered)
4	LATCH	data strobe input (active high)
5	OUT0	current-sinking output
6	OUT1	current-sinking output
7	OUT2	current-sinking output
8	OUT3	current-sinking output
9	OUT4	current-sinking output
10	OUT5	current-sinking output
11	OUT6	current-sinking output
12	OUT7	current-sinking output
13	OUT8	current-sinking output
14	OUT9	current-sinking output
15	OUT10	current-sinking output
16	OUT11	current-sinking output
17	OUT12	current-sinking output
18	OUT13	current-sinking output
19	OUT14	current-sinking output
20	OUT15	current-sinking output
21	OE	output enable (active low)
22	DATA OUT	serial data out, for cascading
23	REXT	external resistor to ground (sets output current)
24	Vcc	supply voltage

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

AD7528 - CMOS dual 8-bit buffered multiplying DAC - msarnoff.org ChipDB

AD7528

CMOS dual 8-bit buffered multiplying DAC


AGND	1 •	20	OUT B
OUT A	2	19	R_FB B
R_FB A	3	18	V_REF B
V_REF A	4	17	V_DD
DGND	5	16	WR
DACA/DACB	6	15	CS
(MSB) DB7	7	14	DB0 (LSB)
DB6	8	13	DB1
DB5	9	12	DB2
DB4	10	11	DB3

Pin	Symbol	Description
1	AGND	analog ground
2	OUT A	analog current output
3	R_FB A	feedback resistor connection
4	V_REF A	input reference voltage
5	DGND	digital ground
6	DACA/DACB	DAC select
7	(MSB) DB7	parallel data input
8	DB6	parallel data input
9	DB5	parallel data input
10	DB4	parallel data input
11	DB3	parallel data input
12	DB2	parallel data input
13	DB1	parallel data input
14	DB0 (LSB)	parallel data input
15	CS	chip select (active low)
16	WR	write to data register (active low)
17	V_DD	supply voltage
18	V_REF B	input reference voltage
19	R_FB B	feedback resistor connection
20	OUT B	analog current output

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Settling time, V_DD = 5V	400 (AD7528) 100 (TLC7528)	ns
Update rate, V_DD = 5V	2.5 (AD7528) 10 (TLC7528)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

AD7805 - +3.3V to +5V quad 10-bit DAC - msarnoff.org ChipDB

AD7805

+3.3V to +5V quad 10-bit DAC


AGND	1 •	28	AV_DD
V_OUT B	2	27	V_OUT C
V_OUT A	3	26	V_OUT D
REFOUT	4	25	COMP
DB9	5	24	REFIN
DB8	6	23	MODE
DB7	7	22	A0
DB6	8	21	A1
DB5	9	20	DB0
DB4	10	19	DB1
LDAC	11	18	CLR
DB3	12	17	CS
DB2	13	16	WR
DGND	14	15	DV_DD

Pin	Symbol	Description
1	AGND	analog ground
2	V_OUT B	analog output voltage
3	V_OUT A	analog output voltage
4	REFOUT	reference output (typically 1.23V)
5	DB9	parallel data input
6	DB8	parallel data input
7	DB7	parallel data input
8	DB6	parallel data input
9	DB5	parallel data input
10	DB4	parallel data input
11	LDAC	DAC register update (active low)
12	DB3	parallel data input
13	DB2	parallel data input
14	DGND	digital ground
15	DV_DD	digital power supply
16	WR	write to data register (active low)
17	CS	chip select (active low)
18	CLR	asynchronous clear (active low)
19	DB1	parallel data input
20	DB0	parallel data input
21	A1	DAC address input
22	A0	DAC address input
23	MODE	mode input
24	REFIN	external reference input
25	COMP	compensation pin
26	V_OUT D	analog output voltge
27	V_OUT C	analog output voltage
28	AV_DD	analog power supply

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Slew rate	2.5	V/µs
Settling time	1.5	µs
Update rate	667	kHz
Output voltage range, twos complement coding	Vbias ± 15/16*Vbias
Output voltage range, offset binary coding	Vbias/16 to 31/16*Vbias

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

ADC0808 - 8-bit A/D converter with 8-channel multiplexer - msarnoff.org ChipDB

ADC0808

8-bit A/D converter with 8-channel multiplexer


IN3	1 •	28	IN2
IN4	2	27	IN1
IN5	3	26	IN0
IN6	4	25	A0
IN7	5	24	A1
START	6	23	A2
EOC	7	22	ALE
D3	8	21	D7
OUTPUT ENABLE	9	20	D6
CLOCK	10	19	D5
V_CC	11	18	D4
V_REF(+)	12	17	D0
GND	13	16	V_REF(-)
D1	14	15	D2

Pin	Symbol	Description
1	IN3	analog input 3
2	IN4	analog input 4
3	IN5	analog input 5
4	IN6	analog input 6
5	IN7	analog input 7
6	START	start conversion (active high)
7	EOC	end of conversion (active high)
8	D3	data bus
9	OUTPUT ENABLE	data output enable
10	CLOCK	clock input
11	V_CC	supply voltage
12	V_REF(+)	positive voltage reference
13	GND	ground
14	D1	data bus
15	D2	data bus
16	V_REF(-)	negative voltage reference
17	D0	data bus (LSB)
18	D4	data bus
19	D5	data bus
20	D6	data bus
21	D7	data bus (MSB)
22	ALE	address latch enable (positive-edge trigger)
23	A2	channel select (MSB)
24	A1	channel select
25	A0	channel select (LSB)
26	IN0	analog channel 0
27	IN1	analog channel 1
28	IN2	analog channel 2

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Supply voltage V_CC	5	V
Total unadjusted error	±1/2 (ADC0808) ±1 (ADC0809)	LSB
Input resistance, V_REF(+) to V_REF(-)	2.5	kΩ
Analog input voltage range	GND-0.10 (min) Vcc+0.10 (max)	V
Minimum START pulse width	100	ns
Minimum ALE pulse width	100	ns
Analog mux delay time from ALE	1	µs
Conversion time (640 kHz clock frequency)	100	µs
Clock frequency	10 (min) 640 (typical) 1280 (max)	kHz

Notes

The ADC0808 is a more accurate version of the ADC0809.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

ADC0808 - 8-bit A/D converter with 8-channel multiplexer - msarnoff.org ChipDB

ADC0808

8-bit A/D converter with 8-channel multiplexer


IN3	1 •	28	IN2
IN4	2	27	IN1
IN5	3	26	IN0
IN6	4	25	A0
IN7	5	24	A1
START	6	23	A2
EOC	7	22	ALE
D3	8	21	D7
OUTPUT ENABLE	9	20	D6
CLOCK	10	19	D5
V_CC	11	18	D4
V_REF(+)	12	17	D0
GND	13	16	V_REF(-)
D1	14	15	D2

Pin	Symbol	Description
1	IN3	analog input 3
2	IN4	analog input 4
3	IN5	analog input 5
4	IN6	analog input 6
5	IN7	analog input 7
6	START	start conversion (active high)
7	EOC	end of conversion (active high)
8	D3	data bus
9	OUTPUT ENABLE	data output enable
10	CLOCK	clock input
11	V_CC	supply voltage
12	V_REF(+)	positive voltage reference
13	GND	ground
14	D1	data bus
15	D2	data bus
16	V_REF(-)	negative voltage reference
17	D0	data bus (LSB)
18	D4	data bus
19	D5	data bus
20	D6	data bus
21	D7	data bus (MSB)
22	ALE	address latch enable (positive-edge trigger)
23	A2	channel select (MSB)
24	A1	channel select
25	A0	channel select (LSB)
26	IN0	analog channel 0
27	IN1	analog channel 1
28	IN2	analog channel 2

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Supply voltage V_CC	5	V
Total unadjusted error	±1/2 (ADC0808) ±1 (ADC0809)	LSB
Input resistance, V_REF(+) to V_REF(-)	2.5	kΩ
Analog input voltage range	GND-0.10 (min) Vcc+0.10 (max)	V
Minimum START pulse width	100	ns
Minimum ALE pulse width	100	ns
Analog mux delay time from ALE	1	µs
Conversion time (640 kHz clock frequency)	100	µs
Clock frequency	10 (min) 640 (typical) 1280 (max)	kHz

Notes

The ADC0808 is a more accurate version of the ADC0809.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

628512 - 512K x 8 static RAM - msarnoff.org ChipDB

628512

512K x 8 static RAM


A₁₈	1 •	32	Vcc
A₁₆	2	31	A₁₅
A₁₄	3	30	A₁₇
A₁₂	4	29	WE
A₇	5	28	A₁₃
A₆	6	27	A₈
A₅	7	26	A₉
A₄	8	25	A₁₁
A₃	9	24	OE
A₂	10	23	A₁₀
A₁	11	22	CS
A₀	12	21	I/O₇
I/O₀	13	20	I/O₆
I/O₁	14	19	I/O₅
I/O₂	15	18	I/O₄
GND	16	17	I/O₃

Pin	Symbol	Description
1	A₁₈	address input
2	A₁₆	address input
3	A₁₄	address input
4	A₁₂	address input
5	A₇	address input
6	A₆	address input
7	A₅	address input
8	A₄	address input
9	A₃	address input
10	A₂	address input
11	A₁	address input
12	A₀	address input
13	I/O₀	data input/output
14	I/O₁	data input/output
15	I/O₂	data input/output
16	GND	ground
17	I/O₃	data input/output
18	I/O₄	data input/output
19	I/O₅	data input/output
20	I/O₆	data input/output
21	I/O₇	data input/output
22	CS	chip select (active low)
23	A₁₀	address input
24	OE	output enable (active low)
25	A₁₁	address input
26	A₉	address input
27	A₈	address input
28	A₁₃	address input
29	WE	write enable (active low)
30	A₁₇	address input
31	A₁₅	address input
32	Vcc	supply voltage

Notes

Data is written when CS is low and WE is low.

Data is read when CS is low, OE is low, and WE is high.

The input/output pins assume a high-impedance state if CS is high.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

ATmega32 - 8-bit AVR® microcontroller - msarnoff.org ChipDB

ATmega32

8-bit AVR® microcontroller


(XCK0/T0) PB0	1 •	40	PA0 (ADC0)
(T1) PB1	2	39	PA1 (ADC1)
(INT2/AIN0) PB2	3	38	PA2 (ADC2)
(OC0/AIN1) PB3	4	37	PA3 (ADC3)
(SS) PB4	5	36	PA4 (ADC4)
(MOSI) PB5	6	35	PA5 (ADC5)
(MISO) PB6	7	34	PA6 (ADC6)
(SCK) PB7	8	33	PA7 (ADC7)
RESET	9	32	AREF
Vcc	10	31	GND
GND	11	30	AVcc
XTAL2	12	29	PC7 (TOSC2)
XTAL1	13	28	PC6 (TOSC1)
(RXD) PD0	14	27	PC5 (TDI)
(TXD) PD1	15	26	PC4 (TDO)
(INT0) PD2	16	25	PC3 (TMS)
(INT1) PD3	17	24	PC2 (TCK)
(OC1B) PD4	18	23	PC1 (SDA)
(OC1A) PD5	19	22	PC0 (SCL)
(ICP1) PD6	20	21	PD7 (OC2)

Pin	Symbol	Description
1	(XCK0/T0) PB0	port B
2	(T1) PB1	port B
3	(INT2/AIN0) PB2	external interrupt 2; port B
4	(OC0/AIN1) PB3	port B
5	(SS) PB4	SPI slave select; port B
6	(MOSI) PB5	SPI master output/slave input; port B
7	(MISO) PB6	SPI master input/slave output; port B
8	(SCK) PB7	SPI master clock; port B
9	RESET	reset (active low)
10	Vcc	supply voltage
11	GND	ground
12	XTAL2	clock oscillator pin 2
13	XTAL1	clock oscillator pin 1
14	(RXD) PD0	UART receive; port D
15	(TXD) PD1	UART transmit; port D
16	(INT0) PD2	external interrupt 0; port D
17	(INT1) PD3	external interrupt 1; port D
18	(OC1B) PD4	port D
19	(OC1A) PD5	port D
20	(ICP1) PD6	port D
21	PD7 (OC2)	port D
22	PC0 (SCL)	2-wire clock line; port C
23	PC1 (SDA)	2-wire data line; port C
24	PC2 (TCK)	JTAG test clock; port C
25	PC3 (TMS)	JTAG test mode select; port C
26	PC4 (TDO)	JTAG test data output; port C
27	PC5 (TDI)	JTAG test data input; port C
28	PC6 (TOSC1)	timer oscillator pin 1; port C
29	PC7 (TOSC2)	timer oscillator pin 2; port C
30	AVcc	A/D converter supply voltage
31	GND	ground
32	AREF	analog reference for A/D converter
33	PA7 (ADC7)	port A
34	PA6 (ADC6)	port A
35	PA5 (ADC5)	port A
36	PA4 (ADC4)	port A
37	PA3 (ADC3)	port A
38	PA2 (ADC2)	port A
39	PA1 (ADC1)	port A
40	PA0 (ADC0)	port A

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Flash memory	16K (ATmega16) 32K (ATmega32)	bytes
Internal SRAM	1K (ATmega16) 2K (ATmega32)	bytes
EEPROM	512 (ATmega16) 1K (ATmega32)	bytes
Programmable I/O lines	32

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

ATmega168 - 8-bit AVR® microcontroller - msarnoff.org ChipDB

ATmega168

8-bit AVR® microcontroller


(PCINT14/RESET) PC6	1 •	28	PC5 (ADC5/SCL/PCINT13)
(PCINT16/RXD) PD0	2	27	PC4 (ADC4/SDA/PCINT12)
(PCINT17/TXD) PD1	3	26	PC3 (ADC3/PCINT11)
(PCINT18/INT0) PD2	4	25	PC2 (ADC2/PCINT10)
(PCINT19/OC2B/INT1) PD3	5	24	PC1 (ADC1/PCINT9)
(PCINT20/XCK/T0) PD4	6	23	PC0 (ADC0/PCINT8)
Vcc	7	22	GND
GND	8	21	AREF
(PCINT6/XTAL1/TOSC1) PB6	9	20	AVcc
(PCINT17/XTAL2/TOSC2) PB7	10	19	PB5 (SCK/PCINT5)
(PCINT21/OC0B/T1) PD5	11	18	PB4 (MISO/PCINT4)
(PCINT22/OC0A/AIN0) PD6	12	17	PB3 (MOSI/OC2A/PCINT3)
(PCINT23/AIN1) PD7	13	16	PB2 (SS/OC1B/PCINT2)
(PCINT0/CLKO/ICP1) PB0	14	15	PB1 (OC1A/PCINT1)

Pin	Symbol	Description
1	(PCINT14/RESET) PC6	reset (active low); port C
2	(PCINT16/RXD) PD0	port D
3	(PCINT17/TXD) PD1	port D
4	(PCINT18/INT0) PD2	external interrupt 0; port D
5	(PCINT19/OC2B/INT1) PD3	external interrupt 1; port D
6	(PCINT20/XCK/T0) PD4	port D
7	Vcc	supply voltage
8	GND	ground
9	(PCINT6/XTAL1/TOSC1) PB6	clock oscillator pin 1; port B
10	(PCINT17/XTAL2/TOSC2) PB7	clock oscillator pin 2; port B
11	(PCINT21/OC0B/T1) PD5	port D
12	(PCINT22/OC0A/AIN0) PD6	port D
13	(PCINT23/AIN1) PD7	port D
14	(PCINT0/CLKO/ICP1) PB0	clock output; port B
15	PB1 (OC1A/PCINT1)	port B
16	PB2 (SS/OC1B/PCINT2)	SPI slave select; port B
17	PB3 (MOSI/OC2A/PCINT3)	SPI master output/slave input; port B
18	PB4 (MISO/PCINT4)	SPI master input/slave output; port B
19	PB5 (SCK/PCINT5)	SPI master clock; port B
20	AVcc	A/D converter supply voltage
21	AREF	analog reference for A/D converter
22	GND	ground
23	PC0 (ADC0/PCINT8)	port C
24	PC1 (ADC1/PCINT9)	port C
25	PC2 (ADC2/PCINT10)	port C
26	PC3 (ADC3/PCINT11)	port C
27	PC4 (ADC4/SDA/PCINT12)	I2C Data pin; port C
28	PC5 (ADC5/SCL/PCINT13)	I2C Clock pin; port C

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Flash memory	4K (ATmega48) 8K (ATmega88) 16K (ATmega168) 32K (ATmega328P)	bytes
Internal SRAM	512 (ATmega48) 1K (ATmega88) 1K (ATmega168) 2K (ATmega328P)	bytes
EEPROM	256 (ATmega48) 512 (ATmega88) 512 (ATmega168) 1K (ATmega328P)	bytes
Programmable I/O lines	23
Maximum clock frequency	20	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

ATmega32 - 8-bit AVR® microcontroller - msarnoff.org ChipDB

ATmega32

8-bit AVR® microcontroller


(XCK0/T0) PB0	1 •	40	PA0 (ADC0)
(T1) PB1	2	39	PA1 (ADC1)
(INT2/AIN0) PB2	3	38	PA2 (ADC2)
(OC0/AIN1) PB3	4	37	PA3 (ADC3)
(SS) PB4	5	36	PA4 (ADC4)
(MOSI) PB5	6	35	PA5 (ADC5)
(MISO) PB6	7	34	PA6 (ADC6)
(SCK) PB7	8	33	PA7 (ADC7)
RESET	9	32	AREF
Vcc	10	31	GND
GND	11	30	AVcc
XTAL2	12	29	PC7 (TOSC2)
XTAL1	13	28	PC6 (TOSC1)
(RXD) PD0	14	27	PC5 (TDI)
(TXD) PD1	15	26	PC4 (TDO)
(INT0) PD2	16	25	PC3 (TMS)
(INT1) PD3	17	24	PC2 (TCK)
(OC1B) PD4	18	23	PC1 (SDA)
(OC1A) PD5	19	22	PC0 (SCL)
(ICP1) PD6	20	21	PD7 (OC2)

Pin	Symbol	Description
1	(XCK0/T0) PB0	port B
2	(T1) PB1	port B
3	(INT2/AIN0) PB2	external interrupt 2; port B
4	(OC0/AIN1) PB3	port B
5	(SS) PB4	SPI slave select; port B
6	(MOSI) PB5	SPI master output/slave input; port B
7	(MISO) PB6	SPI master input/slave output; port B
8	(SCK) PB7	SPI master clock; port B
9	RESET	reset (active low)
10	Vcc	supply voltage
11	GND	ground
12	XTAL2	clock oscillator pin 2
13	XTAL1	clock oscillator pin 1
14	(RXD) PD0	UART receive; port D
15	(TXD) PD1	UART transmit; port D
16	(INT0) PD2	external interrupt 0; port D
17	(INT1) PD3	external interrupt 1; port D
18	(OC1B) PD4	port D
19	(OC1A) PD5	port D
20	(ICP1) PD6	port D
21	PD7 (OC2)	port D
22	PC0 (SCL)	2-wire clock line; port C
23	PC1 (SDA)	2-wire data line; port C
24	PC2 (TCK)	JTAG test clock; port C
25	PC3 (TMS)	JTAG test mode select; port C
26	PC4 (TDO)	JTAG test data output; port C
27	PC5 (TDI)	JTAG test data input; port C
28	PC6 (TOSC1)	timer oscillator pin 1; port C
29	PC7 (TOSC2)	timer oscillator pin 2; port C
30	AVcc	A/D converter supply voltage
31	GND	ground
32	AREF	analog reference for A/D converter
33	PA7 (ADC7)	port A
34	PA6 (ADC6)	port A
35	PA5 (ADC5)	port A
36	PA4 (ADC4)	port A
37	PA3 (ADC3)	port A
38	PA2 (ADC2)	port A
39	PA1 (ADC1)	port A
40	PA0 (ADC0)	port A

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Flash memory	16K (ATmega16) 32K (ATmega32)	bytes
Internal SRAM	1K (ATmega16) 2K (ATmega32)	bytes
EEPROM	512 (ATmega16) 1K (ATmega32)	bytes
Programmable I/O lines	32

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

ATmega168 - 8-bit AVR® microcontroller - msarnoff.org ChipDB

ATmega168

8-bit AVR® microcontroller


(PCINT14/RESET) PC6	1 •	28	PC5 (ADC5/SCL/PCINT13)
(PCINT16/RXD) PD0	2	27	PC4 (ADC4/SDA/PCINT12)
(PCINT17/TXD) PD1	3	26	PC3 (ADC3/PCINT11)
(PCINT18/INT0) PD2	4	25	PC2 (ADC2/PCINT10)
(PCINT19/OC2B/INT1) PD3	5	24	PC1 (ADC1/PCINT9)
(PCINT20/XCK/T0) PD4	6	23	PC0 (ADC0/PCINT8)
Vcc	7	22	GND
GND	8	21	AREF
(PCINT6/XTAL1/TOSC1) PB6	9	20	AVcc
(PCINT17/XTAL2/TOSC2) PB7	10	19	PB5 (SCK/PCINT5)
(PCINT21/OC0B/T1) PD5	11	18	PB4 (MISO/PCINT4)
(PCINT22/OC0A/AIN0) PD6	12	17	PB3 (MOSI/OC2A/PCINT3)
(PCINT23/AIN1) PD7	13	16	PB2 (SS/OC1B/PCINT2)
(PCINT0/CLKO/ICP1) PB0	14	15	PB1 (OC1A/PCINT1)

Pin	Symbol	Description
1	(PCINT14/RESET) PC6	reset (active low); port C
2	(PCINT16/RXD) PD0	port D
3	(PCINT17/TXD) PD1	port D
4	(PCINT18/INT0) PD2	external interrupt 0; port D
5	(PCINT19/OC2B/INT1) PD3	external interrupt 1; port D
6	(PCINT20/XCK/T0) PD4	port D
7	Vcc	supply voltage
8	GND	ground
9	(PCINT6/XTAL1/TOSC1) PB6	clock oscillator pin 1; port B
10	(PCINT17/XTAL2/TOSC2) PB7	clock oscillator pin 2; port B
11	(PCINT21/OC0B/T1) PD5	port D
12	(PCINT22/OC0A/AIN0) PD6	port D
13	(PCINT23/AIN1) PD7	port D
14	(PCINT0/CLKO/ICP1) PB0	clock output; port B
15	PB1 (OC1A/PCINT1)	port B
16	PB2 (SS/OC1B/PCINT2)	SPI slave select; port B
17	PB3 (MOSI/OC2A/PCINT3)	SPI master output/slave input; port B
18	PB4 (MISO/PCINT4)	SPI master input/slave output; port B
19	PB5 (SCK/PCINT5)	SPI master clock; port B
20	AVcc	A/D converter supply voltage
21	AREF	analog reference for A/D converter
22	GND	ground
23	PC0 (ADC0/PCINT8)	port C
24	PC1 (ADC1/PCINT9)	port C
25	PC2 (ADC2/PCINT10)	port C
26	PC3 (ADC3/PCINT11)	port C
27	PC4 (ADC4/SDA/PCINT12)	I2C Data pin; port C
28	PC5 (ADC5/SCL/PCINT13)	I2C Clock pin; port C

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Flash memory	4K (ATmega48) 8K (ATmega88) 16K (ATmega168) 32K (ATmega328P)	bytes
Internal SRAM	512 (ATmega48) 1K (ATmega88) 1K (ATmega168) 2K (ATmega328P)	bytes
EEPROM	256 (ATmega48) 512 (ATmega88) 512 (ATmega168) 1K (ATmega328P)	bytes
Programmable I/O lines	23
Maximum clock frequency	20	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

ATmega168 - 8-bit AVR® microcontroller - msarnoff.org ChipDB

ATmega168

8-bit AVR® microcontroller


(PCINT14/RESET) PC6	1 •	28	PC5 (ADC5/SCL/PCINT13)
(PCINT16/RXD) PD0	2	27	PC4 (ADC4/SDA/PCINT12)
(PCINT17/TXD) PD1	3	26	PC3 (ADC3/PCINT11)
(PCINT18/INT0) PD2	4	25	PC2 (ADC2/PCINT10)
(PCINT19/OC2B/INT1) PD3	5	24	PC1 (ADC1/PCINT9)
(PCINT20/XCK/T0) PD4	6	23	PC0 (ADC0/PCINT8)
Vcc	7	22	GND
GND	8	21	AREF
(PCINT6/XTAL1/TOSC1) PB6	9	20	AVcc
(PCINT17/XTAL2/TOSC2) PB7	10	19	PB5 (SCK/PCINT5)
(PCINT21/OC0B/T1) PD5	11	18	PB4 (MISO/PCINT4)
(PCINT22/OC0A/AIN0) PD6	12	17	PB3 (MOSI/OC2A/PCINT3)
(PCINT23/AIN1) PD7	13	16	PB2 (SS/OC1B/PCINT2)
(PCINT0/CLKO/ICP1) PB0	14	15	PB1 (OC1A/PCINT1)

Pin	Symbol	Description
1	(PCINT14/RESET) PC6	reset (active low); port C
2	(PCINT16/RXD) PD0	port D
3	(PCINT17/TXD) PD1	port D
4	(PCINT18/INT0) PD2	external interrupt 0; port D
5	(PCINT19/OC2B/INT1) PD3	external interrupt 1; port D
6	(PCINT20/XCK/T0) PD4	port D
7	Vcc	supply voltage
8	GND	ground
9	(PCINT6/XTAL1/TOSC1) PB6	clock oscillator pin 1; port B
10	(PCINT17/XTAL2/TOSC2) PB7	clock oscillator pin 2; port B
11	(PCINT21/OC0B/T1) PD5	port D
12	(PCINT22/OC0A/AIN0) PD6	port D
13	(PCINT23/AIN1) PD7	port D
14	(PCINT0/CLKO/ICP1) PB0	clock output; port B
15	PB1 (OC1A/PCINT1)	port B
16	PB2 (SS/OC1B/PCINT2)	SPI slave select; port B
17	PB3 (MOSI/OC2A/PCINT3)	SPI master output/slave input; port B
18	PB4 (MISO/PCINT4)	SPI master input/slave output; port B
19	PB5 (SCK/PCINT5)	SPI master clock; port B
20	AVcc	A/D converter supply voltage
21	AREF	analog reference for A/D converter
22	GND	ground
23	PC0 (ADC0/PCINT8)	port C
24	PC1 (ADC1/PCINT9)	port C
25	PC2 (ADC2/PCINT10)	port C
26	PC3 (ADC3/PCINT11)	port C
27	PC4 (ADC4/SDA/PCINT12)	I2C Data pin; port C
28	PC5 (ADC5/SCL/PCINT13)	I2C Clock pin; port C

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Flash memory	4K (ATmega48) 8K (ATmega88) 16K (ATmega168) 32K (ATmega328P)	bytes
Internal SRAM	512 (ATmega48) 1K (ATmega88) 1K (ATmega168) 2K (ATmega328P)	bytes
EEPROM	256 (ATmega48) 512 (ATmega88) 512 (ATmega168) 1K (ATmega328P)	bytes
Programmable I/O lines	23
Maximum clock frequency	20	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

ATmega8 - 8-bit AVR® microcontroller - msarnoff.org ChipDB

ATmega8

8-bit AVR® microcontroller


(RESET) PC6	1 •	28	PC5 (ADC5/SDA)
(RXD) PD0	2	27	PC4 (ADC4/SCL)
(TXD) PD1	3	26	PC3 (ADC3)
(INT0) PD2	4	25	PC2 (ADC2)
(INT1) PD3	5	24	PC1 (ADC1)
(XCK/T0) PD4	6	23	PC0 (ADC0)
Vcc	7	22	GND
GND	8	21	AREF
(XTAL1/TOSC1) PB6	9	20	AVcc
(XTAL2/TOSC2) PB7	10	19	PB5 (SCK)
(T1) PD5	11	18	PB4 (MISO)
(AIN0) PD6	12	17	PB3 (MOSI/OC2)
(AIN1) PD7	13	16	PB2 (SS/OC1B)
(ICP1) PB0	14	15	PB1 (OC1A)

Pin	Symbol	Description
1	(RESET) PC6	reset (active low); port C
2	(RXD) PD0	UART receive; port D
3	(TXD) PD1	UART transmit; port D
4	(INT0) PD2	external interrupt 0; port D
5	(INT1) PD3	external interrupt 1; port D
6	(XCK/T0) PD4	port D
7	Vcc	supply voltage
8	GND	ground
9	(XTAL1/TOSC1) PB6	clock oscillator pin 1; port B
10	(XTAL2/TOSC2) PB7	clock oscillator pin 2; port B
11	(T1) PD5	port D
12	(AIN0) PD6	port D
13	(AIN1) PD7	port D
14	(ICP1) PB0	port B
15	PB1 (OC1A)	port B
16	PB2 (SS/OC1B)	SPI slave select; port B
17	PB3 (MOSI/OC2)	SPI master output/slave input; port B
18	PB4 (MISO)	SPI master input/slave output; port B
19	PB5 (SCK)	SPI master clock; port B
20	AVcc	A/D converter supply voltage
21	AREF	analog reference for A/D converter
22	GND	ground
23	PC0 (ADC0)	port C
24	PC1 (ADC1)	port C
25	PC2 (ADC2)	port C
26	PC3 (ADC3)	port C
27	PC4 (ADC4/SCL)	2-wire clock; port C
28	PC5 (ADC5/SDA)	2-wire data; port C

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Flash memory	8K	bytes
Internal SRAM	1K	bytes
EEPROM	512	bytes
Programmable I/O lines	23
Maximum clock frequency	16	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

ATmega168 - 8-bit AVR® microcontroller - msarnoff.org ChipDB

ATmega168

8-bit AVR® microcontroller


(PCINT14/RESET) PC6	1 •	28	PC5 (ADC5/SCL/PCINT13)
(PCINT16/RXD) PD0	2	27	PC4 (ADC4/SDA/PCINT12)
(PCINT17/TXD) PD1	3	26	PC3 (ADC3/PCINT11)
(PCINT18/INT0) PD2	4	25	PC2 (ADC2/PCINT10)
(PCINT19/OC2B/INT1) PD3	5	24	PC1 (ADC1/PCINT9)
(PCINT20/XCK/T0) PD4	6	23	PC0 (ADC0/PCINT8)
Vcc	7	22	GND
GND	8	21	AREF
(PCINT6/XTAL1/TOSC1) PB6	9	20	AVcc
(PCINT17/XTAL2/TOSC2) PB7	10	19	PB5 (SCK/PCINT5)
(PCINT21/OC0B/T1) PD5	11	18	PB4 (MISO/PCINT4)
(PCINT22/OC0A/AIN0) PD6	12	17	PB3 (MOSI/OC2A/PCINT3)
(PCINT23/AIN1) PD7	13	16	PB2 (SS/OC1B/PCINT2)
(PCINT0/CLKO/ICP1) PB0	14	15	PB1 (OC1A/PCINT1)

Pin	Symbol	Description
1	(PCINT14/RESET) PC6	reset (active low); port C
2	(PCINT16/RXD) PD0	port D
3	(PCINT17/TXD) PD1	port D
4	(PCINT18/INT0) PD2	external interrupt 0; port D
5	(PCINT19/OC2B/INT1) PD3	external interrupt 1; port D
6	(PCINT20/XCK/T0) PD4	port D
7	Vcc	supply voltage
8	GND	ground
9	(PCINT6/XTAL1/TOSC1) PB6	clock oscillator pin 1; port B
10	(PCINT17/XTAL2/TOSC2) PB7	clock oscillator pin 2; port B
11	(PCINT21/OC0B/T1) PD5	port D
12	(PCINT22/OC0A/AIN0) PD6	port D
13	(PCINT23/AIN1) PD7	port D
14	(PCINT0/CLKO/ICP1) PB0	clock output; port B
15	PB1 (OC1A/PCINT1)	port B
16	PB2 (SS/OC1B/PCINT2)	SPI slave select; port B
17	PB3 (MOSI/OC2A/PCINT3)	SPI master output/slave input; port B
18	PB4 (MISO/PCINT4)	SPI master input/slave output; port B
19	PB5 (SCK/PCINT5)	SPI master clock; port B
20	AVcc	A/D converter supply voltage
21	AREF	analog reference for A/D converter
22	GND	ground
23	PC0 (ADC0/PCINT8)	port C
24	PC1 (ADC1/PCINT9)	port C
25	PC2 (ADC2/PCINT10)	port C
26	PC3 (ADC3/PCINT11)	port C
27	PC4 (ADC4/SDA/PCINT12)	I2C Data pin; port C
28	PC5 (ADC5/SCL/PCINT13)	I2C Clock pin; port C

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Flash memory	4K (ATmega48) 8K (ATmega88) 16K (ATmega168) 32K (ATmega328P)	bytes
Internal SRAM	512 (ATmega48) 1K (ATmega88) 1K (ATmega168) 2K (ATmega328P)	bytes
EEPROM	256 (ATmega48) 512 (ATmega88) 512 (ATmega168) 1K (ATmega328P)	bytes
Programmable I/O lines	23
Maximum clock frequency	20	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

ATTiny12 - 8-Bit AVR® microcontroller with 1 kb In-system programmable flash memory - msarnoff.org ChipDB

ATTiny12

8-Bit AVR® microcontroller with 1 kb In-system programmable flash memory


PB5 / RESET	1 •	8	V_CC
PB3 / XTAL1	2	7	PB2 / T0 / SCK
PB4 / XTAL2	3	6	PB1 / INT0 / AIN1 / MISO
GND	4	5	PB0 / AIN0 / MOSI

Pin	Symbol	Description
1	PB5 / RESET	PB5 / chip reset (active low)
2	PB3 / XTAL1	PB3 / Inverting oscillator amplifier input
3	PB4 / XTAL2	PB4 / Inverting oscillator amplifier output
4	GND	Ground
5	PB0 / AIN0 / MOSI	PB0 / Analog comparator positive input / Serial programming input
6	PB1 / INT0 / AIN1 / MISO	PB1 / External interrupt 0 / Analog comparator negative input / Serial programming input
7	PB2 / T0 / SCK	PB2 / Timer/Counter 0 external counter input / Serial clock
8	V_CC	Supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Flash program memory	1	kb
EEPROM memory	64	bytes
Operating voltage	1.8-5.5 (ATTiny12V-1) 2.7-5.5 (ATTiny12L-4) 4.0-5.5 (ATTiny12-8)	V
Speed grade	0-1.2 (ATTiny12V-1) 0-4 (ATTiny12L-4) 0-8 (ATTiny12-8)	MHz
Active power consumption (at 4 MHz, 3V)	2.2	mA
Idle mode power consumption (at 4 MHz, 3V)	0.5	mA
Power-down mode power consumption (at 4 MHz, 3V)	< 1	µA

Notes

Also availablle in SOIC package (same pinout)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

ATTiny12 - 8-Bit AVR® microcontroller with 1 kb In-system programmable flash memory - msarnoff.org ChipDB

ATTiny12

8-Bit AVR® microcontroller with 1 kb In-system programmable flash memory


PB5 / RESET	1 •	8	V_CC
PB3 / XTAL1	2	7	PB2 / T0 / SCK
PB4 / XTAL2	3	6	PB1 / INT0 / AIN1 / MISO
GND	4	5	PB0 / AIN0 / MOSI

Pin	Symbol	Description
1	PB5 / RESET	PB5 / chip reset (active low)
2	PB3 / XTAL1	PB3 / Inverting oscillator amplifier input
3	PB4 / XTAL2	PB4 / Inverting oscillator amplifier output
4	GND	Ground
5	PB0 / AIN0 / MOSI	PB0 / Analog comparator positive input / Serial programming input
6	PB1 / INT0 / AIN1 / MISO	PB1 / External interrupt 0 / Analog comparator negative input / Serial programming input
7	PB2 / T0 / SCK	PB2 / Timer/Counter 0 external counter input / Serial clock
8	V_CC	Supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Flash program memory	1	kb
EEPROM memory	64	bytes
Operating voltage	1.8-5.5 (ATTiny12V-1) 2.7-5.5 (ATTiny12L-4) 4.0-5.5 (ATTiny12-8)	V
Speed grade	0-1.2 (ATTiny12V-1) 0-4 (ATTiny12L-4) 0-8 (ATTiny12-8)	MHz
Active power consumption (at 4 MHz, 3V)	2.2	mA
Idle mode power consumption (at 4 MHz, 3V)	0.5	mA
Power-down mode power consumption (at 4 MHz, 3V)	< 1	µA

Notes

Also availablle in SOIC package (same pinout)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

ATTiny12 - 8-Bit AVR® microcontroller with 1 kb In-system programmable flash memory - msarnoff.org ChipDB

ATTiny12

8-Bit AVR® microcontroller with 1 kb In-system programmable flash memory


PB5 / RESET	1 •	8	V_CC
PB3 / XTAL1	2	7	PB2 / T0 / SCK
PB4 / XTAL2	3	6	PB1 / INT0 / AIN1 / MISO
GND	4	5	PB0 / AIN0 / MOSI

Pin	Symbol	Description
1	PB5 / RESET	PB5 / chip reset (active low)
2	PB3 / XTAL1	PB3 / Inverting oscillator amplifier input
3	PB4 / XTAL2	PB4 / Inverting oscillator amplifier output
4	GND	Ground
5	PB0 / AIN0 / MOSI	PB0 / Analog comparator positive input / Serial programming input
6	PB1 / INT0 / AIN1 / MISO	PB1 / External interrupt 0 / Analog comparator negative input / Serial programming input
7	PB2 / T0 / SCK	PB2 / Timer/Counter 0 external counter input / Serial clock
8	V_CC	Supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Flash program memory	1	kb
EEPROM memory	64	bytes
Operating voltage	1.8-5.5 (ATTiny12V-1) 2.7-5.5 (ATTiny12L-4) 4.0-5.5 (ATTiny12-8)	V
Speed grade	0-1.2 (ATTiny12V-1) 0-4 (ATTiny12L-4) 0-8 (ATTiny12-8)	MHz
Active power consumption (at 4 MHz, 3V)	2.2	mA
Idle mode power consumption (at 4 MHz, 3V)	0.5	mA
Power-down mode power consumption (at 4 MHz, 3V)	< 1	µA

Notes

Also availablle in SOIC package (same pinout)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

ATTiny12 - 8-Bit AVR® microcontroller with 1 kb In-system programmable flash memory - msarnoff.org ChipDB

ATTiny12

8-Bit AVR® microcontroller with 1 kb In-system programmable flash memory


PB5 / RESET	1 •	8	V_CC
PB3 / XTAL1	2	7	PB2 / T0 / SCK
PB4 / XTAL2	3	6	PB1 / INT0 / AIN1 / MISO
GND	4	5	PB0 / AIN0 / MOSI

Pin	Symbol	Description
1	PB5 / RESET	PB5 / chip reset (active low)
2	PB3 / XTAL1	PB3 / Inverting oscillator amplifier input
3	PB4 / XTAL2	PB4 / Inverting oscillator amplifier output
4	GND	Ground
5	PB0 / AIN0 / MOSI	PB0 / Analog comparator positive input / Serial programming input
6	PB1 / INT0 / AIN1 / MISO	PB1 / External interrupt 0 / Analog comparator negative input / Serial programming input
7	PB2 / T0 / SCK	PB2 / Timer/Counter 0 external counter input / Serial clock
8	V_CC	Supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Flash program memory	1	kb
EEPROM memory	64	bytes
Operating voltage	1.8-5.5 (ATTiny12V-1) 2.7-5.5 (ATTiny12L-4) 4.0-5.5 (ATTiny12-8)	V
Speed grade	0-1.2 (ATTiny12V-1) 0-4 (ATTiny12L-4) 0-8 (ATTiny12-8)	MHz
Active power consumption (at 4 MHz, 3V)	2.2	mA
Idle mode power consumption (at 4 MHz, 3V)	0.5	mA
Power-down mode power consumption (at 4 MHz, 3V)	< 1	µA

Notes

Also availablle in SOIC package (same pinout)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

ATtiny13 - 8-bit AVR® microcontroller - msarnoff.org ChipDB

ATtiny13

8-bit AVR® microcontroller


(PCINT5/RESET/ADC0/dW) PB5	1 •	8	Vcc
(PCINT3/CLKI/ADC3) PB3	2	7	PB2 (SCK/ADC1/T0/PCINT2)
(PCINT4/ADC2) PB4	3	6	PB1 (MISO/AIN1/OC0B/INT0/PCINT1)
GND	4	5	PB0 (MOSI/AIN0/OC0A/PCINT0)

Pin	Symbol	Description
1	(PCINT5/RESET/ADC0/dW) PB5	reset (active low); port B
2	(PCINT3/CLKI/ADC3) PB3	external clock input; port B
3	(PCINT4/ADC2) PB4	port B
4	GND	ground
5	PB0 (MOSI/AIN0/OC0A/PCINT0)	SPI master output/slave input; port B
6	PB1 (MISO/AIN1/OC0B/INT0/PCINT1)	SPI master input/slave output; port B
7	PB2 (SCK/ADC1/T0/PCINT2)	SPI master clock; port B
8	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Flash memory	1K	bytes
Internal SRAM	64	bytes
EEPROM	64	bytes
Programmable I/O lines	6
Maximum clock frequency	10	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

ATtiny2313 - 8-bit AVR® microcontroller - msarnoff.org ChipDB

ATtiny2313

8-bit AVR® microcontroller


(RESET/dW) PA2	1 •	20	Vcc
(RXD) PD0	2	19	PB7 (UCSK/SCL/PCINT7)
(TXD) PD1	3	18	PB6 (MISO/DO/PCINT6)
(XTAL2) PA1	4	17	PB5 (MOSI/DI/SDA/PCINT5)
(XTAL1) PA0	5	16	PB4 (OC1B/PCINT4)
(CKOUT/XCK/INT0) PD2	6	15	PB3 (OC1A/PCINT3)
(INT1) PD3	7	14	PB2 (OC0A/PCINT2)
(T0) PD4	8	13	PB1 (AIN1/PCINT1)
(OC0B/T1) PD5	9	12	PB0 (AIN0/PCINT0)
GND	10	11	PD6 (ICP)

Pin	Symbol	Description
1	(RESET/dW) PA2	reset (active low)
2	(RXD) PD0	UART receive; port D
3	(TXD) PD1	UART transmit; port D
4	(XTAL2) PA1	clock oscillator pin 2; port A
5	(XTAL1) PA0	clock oscillator pin 1; port A
6	(CKOUT/XCK/INT0) PD2	external interrupt 0; clock output; port D
7	(INT1) PD3	external interrupt 1; port D
8	(T0) PD4	port D
9	(OC0B/T1) PD5	port D
10	GND	ground
11	PD6 (ICP)	port D
12	PB0 (AIN0/PCINT0)	port B
13	PB1 (AIN1/PCINT1)	port B
14	PB2 (OC0A/PCINT2)	port B
15	PB3 (OC1A/PCINT3)	port B
16	PB4 (OC1B/PCINT4)	port B
17	PB5 (MOSI/DI/SDA/PCINT5)	3-wire data input; 2-wire data; port B
18	PB6 (MISO/DO/PCINT6)	3-wire data output; port B
19	PB7 (UCSK/SCL/PCINT7)	3-wire clock; 2-wire clock; port B
20	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Flash memory	2K (ATtiny2313) 4K (ATtiny4313)	bytes
Internal SRAM	128 (ATtiny2313) 256 (ATtiny4313)	bytes
EEPROM	128 (ATtiny2313) 256 (ATtiny4313)	bytes
Programmable I/O lines	18
Maximum clock frequency	20	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

ATtiny85 - 8-bit AVR® microcontroller - msarnoff.org ChipDB

ATtiny85

8-bit AVR® microcontroller


(PCINT5/RESET/ADC0/dW) PB5	1 •	8	Vcc
(PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3	2	7	PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)
(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4	3	6	PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)
GND	4	5	PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)

Pin	Symbol	Description
1	(PCINT5/RESET/ADC0/dW) PB5	reset (active low); port B
2	(PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3	crystal connection; external clock input; port B
3	(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4	crystal connection; clock output; port B
4	GND	ground
5	PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)	SPI master output/slave input; 2-wire data; ADC reference; port B
6	PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)	SPI master input/slave output; port B
7	PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)	SPI master clock; 2-wire clock; external interrupt 0; port B
8	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Flash memory	2K (ATtiny25) 4K (ATtiny45) 8K (ATtiny85)	bytes
Internal SRAM	128 (ATtiny25) 256 (ATtiny45) 512 (ATtiny85)	bytes
EEPROM	128 (ATtiny25) 256 (ATtiny45) 512 (ATtiny85)	bytes
Programmable I/O lines	6
Maximum clock frequency	20	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

ATtiny2313 - 8-bit AVR® microcontroller - msarnoff.org ChipDB

ATtiny2313

8-bit AVR® microcontroller


(RESET/dW) PA2	1 •	20	Vcc
(RXD) PD0	2	19	PB7 (UCSK/SCL/PCINT7)
(TXD) PD1	3	18	PB6 (MISO/DO/PCINT6)
(XTAL2) PA1	4	17	PB5 (MOSI/DI/SDA/PCINT5)
(XTAL1) PA0	5	16	PB4 (OC1B/PCINT4)
(CKOUT/XCK/INT0) PD2	6	15	PB3 (OC1A/PCINT3)
(INT1) PD3	7	14	PB2 (OC0A/PCINT2)
(T0) PD4	8	13	PB1 (AIN1/PCINT1)
(OC0B/T1) PD5	9	12	PB0 (AIN0/PCINT0)
GND	10	11	PD6 (ICP)

Pin	Symbol	Description
1	(RESET/dW) PA2	reset (active low)
2	(RXD) PD0	UART receive; port D
3	(TXD) PD1	UART transmit; port D
4	(XTAL2) PA1	clock oscillator pin 2; port A
5	(XTAL1) PA0	clock oscillator pin 1; port A
6	(CKOUT/XCK/INT0) PD2	external interrupt 0; clock output; port D
7	(INT1) PD3	external interrupt 1; port D
8	(T0) PD4	port D
9	(OC0B/T1) PD5	port D
10	GND	ground
11	PD6 (ICP)	port D
12	PB0 (AIN0/PCINT0)	port B
13	PB1 (AIN1/PCINT1)	port B
14	PB2 (OC0A/PCINT2)	port B
15	PB3 (OC1A/PCINT3)	port B
16	PB4 (OC1B/PCINT4)	port B
17	PB5 (MOSI/DI/SDA/PCINT5)	3-wire data input; 2-wire data; port B
18	PB6 (MISO/DO/PCINT6)	3-wire data output; port B
19	PB7 (UCSK/SCL/PCINT7)	3-wire clock; 2-wire clock; port B
20	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Flash memory	2K (ATtiny2313) 4K (ATtiny4313)	bytes
Internal SRAM	128 (ATtiny2313) 256 (ATtiny4313)	bytes
EEPROM	128 (ATtiny2313) 256 (ATtiny4313)	bytes
Programmable I/O lines	18
Maximum clock frequency	20	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

ATtiny85 - 8-bit AVR® microcontroller - msarnoff.org ChipDB

ATtiny85

8-bit AVR® microcontroller


(PCINT5/RESET/ADC0/dW) PB5	1 •	8	Vcc
(PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3	2	7	PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)
(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4	3	6	PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)
GND	4	5	PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)

Pin	Symbol	Description
1	(PCINT5/RESET/ADC0/dW) PB5	reset (active low); port B
2	(PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3	crystal connection; external clock input; port B
3	(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4	crystal connection; clock output; port B
4	GND	ground
5	PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)	SPI master output/slave input; 2-wire data; ADC reference; port B
6	PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)	SPI master input/slave output; port B
7	PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)	SPI master clock; 2-wire clock; external interrupt 0; port B
8	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Flash memory	2K (ATtiny25) 4K (ATtiny45) 8K (ATtiny85)	bytes
Internal SRAM	128 (ATtiny25) 256 (ATtiny45) 512 (ATtiny85)	bytes
EEPROM	128 (ATtiny25) 256 (ATtiny45) 512 (ATtiny85)	bytes
Programmable I/O lines	6
Maximum clock frequency	20	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

ATtiny85 - 8-bit AVR® microcontroller - msarnoff.org ChipDB

ATtiny85

8-bit AVR® microcontroller


(PCINT5/RESET/ADC0/dW) PB5	1 •	8	Vcc
(PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3	2	7	PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)
(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4	3	6	PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)
GND	4	5	PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)

Pin	Symbol	Description
1	(PCINT5/RESET/ADC0/dW) PB5	reset (active low); port B
2	(PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3	crystal connection; external clock input; port B
3	(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4	crystal connection; clock output; port B
4	GND	ground
5	PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)	SPI master output/slave input; 2-wire data; ADC reference; port B
6	PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)	SPI master input/slave output; port B
7	PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)	SPI master clock; 2-wire clock; external interrupt 0; port B
8	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Flash memory	2K (ATtiny25) 4K (ATtiny45) 8K (ATtiny85)	bytes
Internal SRAM	128 (ATtiny25) 256 (ATtiny45) 512 (ATtiny85)	bytes
EEPROM	128 (ATtiny25) 256 (ATtiny45) 512 (ATtiny85)	bytes
Programmable I/O lines	6
Maximum clock frequency	20	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

AY-3-8910 - Programmable sound generator - msarnoff.org ChipDB

AY-3-8910

Programmable sound generator


GND	1 •	40	Vcc
NC	2	39	TEST 1
ANALOG B	3	38	ANALOG C
ANALOG A	4	37	DA0
NC	5	36	DA1
IOB7	6	35	DA2
IOB6	7	34	DA3
IOB5	8	33	DA4
IOB4	9	32	DA5
IOB3	10	31	DA6
IOB2	11	30	DA7
IOB1	12	29	BC1
IOB0	13	28	BC2
IOA7	14	27	BDIR
IOA6	15	26	TEST 2/SEL
IOA5	16	25	A8
IOA4	17	24	A9
IOA3	18	23	RESET
IOA2	19	22	CLOCK
IOA1	20	21	IOA0

Pin	Symbol	Description
1	GND	ground
2	NC	no connection
3	ANALOG B	analog output, channel B
4	ANALOG A	analog output, channel A
5	NC	no connection
6	IOB7	I/O port B
7	IOB6	I/O port B
8	IOB5	I/O port B
9	IOB4	I/O port B
10	IOB3	I/O port B
11	IOB2	I/O port B
12	IOB1	I/O port B
13	IOB0	I/O port B
14	IOA7	I/O port A
15	IOA6	I/O port A
16	IOA5	I/O port A
17	IOA4	I/O port A
18	IOA3	I/O port A
19	IOA2	I/O port A
20	IOA1	I/O port A
21	IOA0	I/O port A
22	CLOCK	clock input
23	RESET	master reset (active low)
24	A9	chip select
25	A8	chip select
26	TEST 2/SEL	test pin (do not connect)
27	BDIR	bus direction
28	BC2	bus control
29	BC1	bus control
30	DA7	data/address bus
31	DA6	data/address bus
32	DA5	data/address bus
33	DA4	data/address bus
34	DA3	data/address bus
35	DA2	data/address bus
36	DA1	data/address bus
37	DA0	data/address bus
38	ANALOG C	analog output, channel C
39	TEST 1	test pin (do not connect)
40	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Minimum clock frequency	1	MHz
Maximum clock frequency	2.5 (AY-3-8910) 4 (YM2149)	MHz

Notes

Chip is only active when A9 is low, A8 is high, and address bits DA7-DA4 are low.

Address bits DA3-DA0 select one of the 16 control registers.

For YM2149, connecting pin 26 to ground divides CLOCK by 2.

BDIR=0, BC2=0, BC1=0: inactive, DA7-DA0 high impedance

BDIR=0, BC2=0, BC1=1: latch address, DA7-DA0 are inputs

BDIR=0, BC2=1, BC1=0: inactive, DA7-DA0 high impedance

BDIR=0, BC2=1, BC1=1: read, DA7-DA0 are outputs

BDIR=1, BC2=0, BC1=0: latch address, DA7-DA0 are inputs

BDIR=1, BC2=0, BC1=1: inactive, DA7-DA0 high impedance

BDIR=1, BC2=1, BC1=0: write, DA7-DA0 are inputs

BDIR=1, BC2=1, BC1=1: latch address, DA7-DA0 are inputs

Control registers:

$00	tone generator A frequency, low 8 bits
$01	tone generator A frequency, high 4 bits
$02	tone generator B frequency, low 8 bits
$03	tone generator B frequency, high 4 bits
$04	tone generator C frequency, low 8 bits
$05	tone generator C frequency, high 4 bits
$06	noise generator frequency, low 5 bits
$07	I/O port and mixer control
$08	channel A amplitude/envelope enable
$09	channel B amplitude/envelope enable
$0A	channel C amplitude/envelope enable
$0B	envelope frequency, low 8 bits
$0C	envelope frequency, high 8 bits
$0D	envelope shape
$0E	I/O port A data
$0F	I/O port B data

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

1802 - CDP1802 CMOS 8-bit microprocessor - msarnoff.org ChipDB

1802

CDP1802 CMOS 8-bit microprocessor


CLOCK	1 •	40	V_DD
WAIT	2	39	XTAL
CLEAR	3	38	DMA_IN
Q	4	37	DMA_OUT
SC1	5	36	INTERRUPT
SC0	6	35	MWR
MRD	7	34	TPA
BUS 7	8	33	TPB
BUS 6	9	32	MA7
BUS 5	10	31	MA6
BUS 4	11	30	MA5
BUS 3	12	29	MA4
BUS 2	13	28	MA3
BUS 1	14	27	MA2
BUS 0	15	26	MA1
V_CC	16	25	MA0
N2	17	24	EF1
N1	18	23	EF2
N0	19	22	EF3
V_SS	20	21	EF4

Pin	Symbol	Description
1	CLOCK	input for externally generated single-phase clock
2	WAIT	control line
3	CLEAR	control line
4	Q	general output
5	SC1	state code
6	SC0	state code
7	MRD	read pulse
8	BUS 7	data bus
9	BUS 6	data bus
10	BUS 5	data bus
11	BUS 4	data bus
12	BUS 3	data bus
13	BUS 2	data bus
14	BUS 1	data bus
15	BUS 0	data bus
16	V_CC	I/O voltage supply
17	N2	I/O control line
18	N1	I/O control line
19	N0	I/O control line
20	V_SS	ground
21	EF4	I/O flag
22	EF3	I/O flag
23	EF2	I/O flag
24	EF1	I/O flag
25	MA0	memory address
26	MA1	memory address
27	MA2	memory address
28	MA3	memory address
29	MA4	memory address
30	MA5	memory address
31	MA6	memory address
32	MA7	memory address
33	TPB	timing pulse
34	TPA	timing pulse
35	MWR	write pulse
36	INTERRUPT	interrupt
37	DMA_OUT	DMA out
38	DMA_IN	DMA in
39	XTAL	crystal input, for on-chip oscillator
40	V_DD	internal voltage supply

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum input clock maximum frequency at 5V	3.2	MHz
Maximum input clock maximum frequency at 10V	6.4	MHz
Minimum instruction fetch-execute time at 5V	5.0	µs

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

1802 - CDP1802 CMOS 8-bit microprocessor - msarnoff.org ChipDB

1802

CDP1802 CMOS 8-bit microprocessor


CLOCK	1 •	40	V_DD
WAIT	2	39	XTAL
CLEAR	3	38	DMA_IN
Q	4	37	DMA_OUT
SC1	5	36	INTERRUPT
SC0	6	35	MWR
MRD	7	34	TPA
BUS 7	8	33	TPB
BUS 6	9	32	MA7
BUS 5	10	31	MA6
BUS 4	11	30	MA5
BUS 3	12	29	MA4
BUS 2	13	28	MA3
BUS 1	14	27	MA2
BUS 0	15	26	MA1
V_CC	16	25	MA0
N2	17	24	EF1
N1	18	23	EF2
N0	19	22	EF3
V_SS	20	21	EF4

Pin	Symbol	Description
1	CLOCK	input for externally generated single-phase clock
2	WAIT	control line
3	CLEAR	control line
4	Q	general output
5	SC1	state code
6	SC0	state code
7	MRD	read pulse
8	BUS 7	data bus
9	BUS 6	data bus
10	BUS 5	data bus
11	BUS 4	data bus
12	BUS 3	data bus
13	BUS 2	data bus
14	BUS 1	data bus
15	BUS 0	data bus
16	V_CC	I/O voltage supply
17	N2	I/O control line
18	N1	I/O control line
19	N0	I/O control line
20	V_SS	ground
21	EF4	I/O flag
22	EF3	I/O flag
23	EF2	I/O flag
24	EF1	I/O flag
25	MA0	memory address
26	MA1	memory address
27	MA2	memory address
28	MA3	memory address
29	MA4	memory address
30	MA5	memory address
31	MA6	memory address
32	MA7	memory address
33	TPB	timing pulse
34	TPA	timing pulse
35	MWR	write pulse
36	INTERRUPT	interrupt
37	DMA_OUT	DMA out
38	DMA_IN	DMA in
39	XTAL	crystal input, for on-chip oscillator
40	V_DD	internal voltage supply

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum input clock maximum frequency at 5V	3.2	MHz
Maximum input clock maximum frequency at 10V	6.4	MHz
Minimum instruction fetch-execute time at 5V	5.0	µs

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

1802 - CDP1802 CMOS 8-bit microprocessor - msarnoff.org ChipDB

1802

CDP1802 CMOS 8-bit microprocessor


CLOCK	1 •	40	V_DD
WAIT	2	39	XTAL
CLEAR	3	38	DMA_IN
Q	4	37	DMA_OUT
SC1	5	36	INTERRUPT
SC0	6	35	MWR
MRD	7	34	TPA
BUS 7	8	33	TPB
BUS 6	9	32	MA7
BUS 5	10	31	MA6
BUS 4	11	30	MA5
BUS 3	12	29	MA4
BUS 2	13	28	MA3
BUS 1	14	27	MA2
BUS 0	15	26	MA1
V_CC	16	25	MA0
N2	17	24	EF1
N1	18	23	EF2
N0	19	22	EF3
V_SS	20	21	EF4

Pin	Symbol	Description
1	CLOCK	input for externally generated single-phase clock
2	WAIT	control line
3	CLEAR	control line
4	Q	general output
5	SC1	state code
6	SC0	state code
7	MRD	read pulse
8	BUS 7	data bus
9	BUS 6	data bus
10	BUS 5	data bus
11	BUS 4	data bus
12	BUS 3	data bus
13	BUS 2	data bus
14	BUS 1	data bus
15	BUS 0	data bus
16	V_CC	I/O voltage supply
17	N2	I/O control line
18	N1	I/O control line
19	N0	I/O control line
20	V_SS	ground
21	EF4	I/O flag
22	EF3	I/O flag
23	EF2	I/O flag
24	EF1	I/O flag
25	MA0	memory address
26	MA1	memory address
27	MA2	memory address
28	MA3	memory address
29	MA4	memory address
30	MA5	memory address
31	MA6	memory address
32	MA7	memory address
33	TPB	timing pulse
34	TPA	timing pulse
35	MWR	write pulse
36	INTERRUPT	interrupt
37	DMA_OUT	DMA out
38	DMA_IN	DMA in
39	XTAL	crystal input, for on-chip oscillator
40	V_DD	internal voltage supply

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum input clock maximum frequency at 5V	3.2	MHz
Maximum input clock maximum frequency at 10V	6.4	MHz
Minimum instruction fetch-execute time at 5V	5.0	µs

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

DS1307 - 64 x 8, serial, I2C real-time clock - msarnoff.org ChipDB

DS1307

64 x 8, serial, I2C real-time clock


X1	1 •	8	Vcc
X2	2	7	SQW/OUT
V_BAT	3	6	SCL
GND	4	5	SDA

Pin	Symbol	Description
1	X1	32.768kHz crystal connection
2	X2	32.768kHz crystal connection
3	V_BAT	backup supply voltage (e.g. 3V lithium coin cell)
4	GND	ground
5	SDA	serial data input/output
6	SCL	serial clock input
7	SQW/OUT	square wave output
8	Vcc	primary supply voltage

Notes

A lithium battery with 48 mAh or greater will back up the DS1307 for more than 10 years.

Square wave output can be 1Hz, 4.096kHz, 8.192kHz, or 32.768kHz.

Reads/writes are inhibited when Vcc falls below 1.25 x V_BAT.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

DS1620 - Digital Thermometer and Thermostat - msarnoff.org ChipDB

DS1620

Digital Thermometer and Thermostat


DQ	1 •	8	V_DD
CLK/CONV	2	7	T_HIGH
RST	3	6	T_LOW
GND	4	5	T_COM

Pin	Symbol	Description
1	DQ	3-Wire input/output
2	CLK/CONV	3-Wire clock input & stand-alone convert input
3	RST	reset
4	GND	power ground
5	T_COM	Hi/Lo combined trigger
6	T_LOW	low Temp trigger
7	T_HIGH	high Temp trigger
8	V_DD	+3V to +5V

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Data resolution	9	Bits
Measurement range	-55 to +125	Deg C
Supply Voltage	3 - 5	Volts

Notes

Temperature excursions beyond user defined Max / Min limits will trigger T_HIGH or T_LOW outputs for application driven temperature correction.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

DS32kHz - 32.768kHz temperature-compensated crystal oscillator - msarnoff.org ChipDB

DS32kHz

32.768kHz temperature-compensated crystal oscillator


NC	1 •	14	NC
	2	13	Vcc
	3	12	32kHz
GND	4	11	NC
V_BAT	5	10	NC
NC	6	9	NC
NC	7	8	NC

Pin	Symbol	Description
1	NC	no connection
2		no pin
3		no pin
4	GND	ground
5	V_BAT	+3V nominal backup supply voltage
6	NC	no connection
7	NC	no connection
8	NC	no connection
9	NC	no connection
10	NC	no connection
11	NC	no connection
12	32kHz	32.768kHz push-pull output
13	Vcc	primary supply voltage
14	NC	no connection

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Frequency stability, 0°C to +40°C	±2.0	ppm
Frequency stability, -40°C to +85°C	±7.5	ppm

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4N35M - Phototransistor output optocoupler - msarnoff.org ChipDB

4N35M

Phototransistor output optocoupler


A	1 •	6	B
K	2	5	C
NC	3	4	E

Pin	Symbol	Description
1	A	anode
2	K	cathode
3	NC	no connection
4	E	emitter
5	C	collector
6	B	base

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Input forward voltage, typical	1.18	V
Input forward voltage, maximum	1.5	V
Input current, maximum	60	ma
Current transfer ratio, collector to emitter	100 (4N35M/4N36M/4N37M) 50 (H11A1M) 30 (H11A5M) 20 (4N25M/4N26M/H11A2M/H11A3M) 10 (4N27M/4N28M/H11A4M)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4N35M - Phototransistor output optocoupler - msarnoff.org ChipDB

4N35M

Phototransistor output optocoupler


A	1 •	6	B
K	2	5	C
NC	3	4	E

Pin	Symbol	Description
1	A	anode
2	K	cathode
3	NC	no connection
4	E	emitter
5	C	collector
6	B	base

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Input forward voltage, typical	1.18	V
Input forward voltage, maximum	1.5	V
Input current, maximum	60	ma
Current transfer ratio, collector to emitter	100 (4N35M/4N36M/4N37M) 50 (H11A1M) 30 (H11A5M) 20 (4N25M/4N26M/H11A2M/H11A3M) 10 (4N27M/4N28M/H11A4M)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4N35M - Phototransistor output optocoupler - msarnoff.org ChipDB

4N35M

Phototransistor output optocoupler


A	1 •	6	B
K	2	5	C
NC	3	4	E

Pin	Symbol	Description
1	A	anode
2	K	cathode
3	NC	no connection
4	E	emitter
5	C	collector
6	B	base

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Input forward voltage, typical	1.18	V
Input forward voltage, maximum	1.5	V
Input current, maximum	60	ma
Current transfer ratio, collector to emitter	100 (4N35M/4N36M/4N37M) 50 (H11A1M) 30 (H11A5M) 20 (4N25M/4N26M/H11A2M/H11A3M) 10 (4N27M/4N28M/H11A4M)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4N35M - Phototransistor output optocoupler - msarnoff.org ChipDB

4N35M

Phototransistor output optocoupler


A	1 •	6	B
K	2	5	C
NC	3	4	E

Pin	Symbol	Description
1	A	anode
2	K	cathode
3	NC	no connection
4	E	emitter
5	C	collector
6	B	base

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Input forward voltage, typical	1.18	V
Input forward voltage, maximum	1.5	V
Input current, maximum	60	ma
Current transfer ratio, collector to emitter	100 (4N35M/4N36M/4N37M) 50 (H11A1M) 30 (H11A5M) 20 (4N25M/4N26M/H11A2M/H11A3M) 10 (4N27M/4N28M/H11A4M)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

4N35M - Phototransistor output optocoupler - msarnoff.org ChipDB

4N35M

Phototransistor output optocoupler


A	1 •	6	B
K	2	5	C
NC	3	4	E

Pin	Symbol	Description
1	A	anode
2	K	cathode
3	NC	no connection
4	E	emitter
5	C	collector
6	B	base

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Input forward voltage, typical	1.18	V
Input forward voltage, maximum	1.5	V
Input current, maximum	60	ma
Current transfer ratio, collector to emitter	100 (4N35M/4N36M/4N37M) 50 (H11A1M) 30 (H11A5M) 20 (4N25M/4N26M/H11A2M/H11A3M) 10 (4N27M/4N28M/H11A4M)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

6N137 - 10 MBit/s single-channel high speed logic gate output optocoupler - msarnoff.org ChipDB
6N137
10 MBit/s single-channel high speed logic gate output optocoupler

N/C 1 • 8 Vcc
V_F + 2 7 V_E
V_F - 3 6 V_O
N/C 4 5 GND

Pin Symbol Description
1 N/C no connection
2 V_F + emitter, anode
3 V_F - emitter, cathode
4 N/C no connection
5 GND supply ground
6 V_O output
7 V_E enable input
8 Vcc supply voltage
Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Supply voltage, minimum 4.5 V
Supply voltage, maxmimum 5.5 V
Input forward voltage, typical @ 25C 1.4 V
Input forward voltage, typical @ 25C 1.4 V
Input forward voltage, max 1.8 V
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.
6N137 - 10 MBit/s single-channel high speed logic gate output optocoupler - msarnoff.org ChipDB
6N137
10 MBit/s single-channel high speed logic gate output optocoupler

N/C 1 • 8 Vcc
V_F + 2 7 V_E
V_F - 3 6 V_O
N/C 4 5 GND

Pin Symbol Description
1 N/C no connection
2 V_F + emitter, anode
3 V_F - emitter, cathode
4 N/C no connection
5 GND supply ground
6 V_O output
7 V_E enable input
8 Vcc supply voltage
Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Supply voltage, minimum 4.5 V
Supply voltage, maxmimum 5.5 V
Input forward voltage, typical @ 25C 1.4 V
Input forward voltage, typical @ 25C 1.4 V
Input forward voltage, max 1.8 V
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

HSN-1000 - Nuclear event detector - msarnoff.org ChipDB

HSN-1000

Nuclear event detector


V_L	1 •	14	V_H
NED	2	13	NC
NC	3	12	NC
CAP1	4	11	NC
CAP2	5	10	NC
BIT	6	9	THR_ADJ
GND	7	8	V_B

Pin	Symbol	Description
1	V_L	load voltage
2	NED	nuclear event detection (active low)
3	NC	no connection
4	CAP1	external capacitor
5	CAP2	external capacitor
6	BIT	built-in test
7	GND	package ground and case
8	V_B	pin diode bias
9	THR_ADJ	threshold adjust
10	NC	no connection
11	NC	no connection
12	NC	no connection
13	NC	no connection
14	V_H	hardened supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Hardened supply voltage	4.5 (min) 5.5 (max)	V
Radiation propagation delay time	20	ns
Dose rate (operate-through)	1 × 10¹²	rad(Si)/s
Total dose	1 × 10⁶	rad(Si)
Neutron fluence	5 × 10¹³	n/cm²
Approximate detection range	2 × 10⁵ (min) 2 × 10⁷ (max)	rad(Si)/s

Notes

Less than a 30% variation in detection threshold can be expected over the entire operating temperature range.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

ICL7660 - Switched-capacitor voltage converter - msarnoff.org ChipDB

ICL7660

Switched-capacitor voltage converter


NC	1 •	8	V+
CAP+	2	7	OSC
GND	3	6	LV
CAP-	4	5	V_OUT

Pin	Symbol	Description
1	NC	no connection
2	CAP+	connection to + terminal of charge-pump capacitor
3	GND	ground
4	CAP-	connection to - terminal of charge-pump capacitor
5	V_OUT	negative voltage output
6	LV	low voltage; connect to ground for V+ < 3.5V
7	OSC	oscillator control input
8	V+	positive supply voltage (1.5V to 10V)

Notes

Basic negative voltage converter: 10µF capacitor across pins 2 and 4; 10µF capacitor across pin 5 (negative lead) and ground (positive lead).

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

ICM7228B - 8-digit LED display decoder/driver, common cathode - msarnoff.org ChipDB

ICM7228B

8-digit LED display decoder/driver, common cathode


DIGIT 4	1 •	28	GND
DIGIT 6	2	27	DIGIT 7
DIGIT 3	3	26	DIGIT 5
DIGIT 1	4	25	DIGIT 2
ID6	5	24	DIGIT 8
ID5	6	23	SEG g
ID7	7	22	SEG f
WRITE	8	21	SEG e
MODE	9	20	SEG c
ID4	10	19	Vcc
ID1	11	18	SEG d
ID0	12	17	SEG b
ID2	13	16	SEG a
ID3	14	15	DP

Pin	Symbol	Description
1	DIGIT 4	digit 4 cathode
2	DIGIT 6	digit 6 cathode
3	DIGIT 3	digit 3 cathode
4	DIGIT 1	digit 1 cathode
5	ID6	data bit 6 (HEXA/CODE-B)
6	ID5	data bit 5 (DECODE)
7	ID7	data bit 7 (DATA COMING)
8	WRITE	write (active low, low-to-high edge triggered)
9	MODE	mode select (control or data word)
10	ID4	data bit 4 (SHUTDOWN)
11	ID1	data bit 1
12	ID0	data bit 0
13	ID2	data bit 2
14	ID3	data bit 3
15	DP	decimal point anode
16	SEG a	segment a anode
17	SEG b	segment b anode
18	SEG d	segment d anode
19	Vcc	supply voltage
20	SEG c	segment c anode
21	SEG e	segment e anode
22	SEG f	segment f anode
23	SEG g	segment g anode
24	DIGIT 8	digit 8 cathode
25	DIGIT 2	digit 2 cathode
26	DIGIT 5	digit 5 cathode
27	DIGIT 7	digit 7 cathode
28	GND	ground

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Display scan rate	390	Hz
Inter-digit blanking time	10	µs
Write pulse width	100 (low) 540 (high)	ns
Mode setup time	150	ns
Data setup time	160	ns
Minimum digit drive capability	50	mA
Segment driver output impedance	100	Ω
Peak current drive per segment	10	mA

Notes

When MODE is low, data is loaded into display RAM. When MODE is high, data is loaded into control register.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

74141 - BCD-to-decimal decoder/Nixie tube driver - msarnoff.org ChipDB
74141
BCD-to-decimal decoder/Nixie tube driver

8 1 • 16 0
9 2 15 1
A 3 14 5
D 4 13 4
Vcc 5 12 GND
B 6 11 6
C 7 10 7
2 8 9 3

Pin Symbol Description
1 8 output 8
2 9 output 9
3 A BCD input
4 D BCD input
5 Vcc supply voltage
6 B BCD input
7 C BCD input
8 2 output 2
9 3 output 3
10 7 output 7
11 6 output 6
12 GND ground
13 4 output 4
14 5 output 5
15 1 output 1
16 0 output 0

Notes
For binary inputs 10 through 15, behavior is manufacturer-specific. 7441s may enable one or more output. 74141s and K155ID1s will turn all outputs off, but the connected tube may not blank.
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

LF347 - Wide bandwidth quad JFET-input operational amplifier - msarnoff.org ChipDB

LF347

Wide bandwidth quad JFET-input operational amplifier


1OUT	1 •	14	4OUT
1IN-	2	13	4IN-
1IN+	3	12	4IN+
Vcc	4	11	Vss
2IN+	5	10	3IN+
2IN-	6	9	3IN-
2OUT	7	8	3OUT

Pin	Symbol	Description
1	1OUT	output 1
2	1IN-	inverting input 1
3	1IN+	non-inverting input 1
4	Vcc	positive supply voltage
5	2IN+	non-inverting input 2
6	2IN-	inverting input 2
7	2OUT	output 2
8	3OUT	output 3
9	3IN-	inverting input 3
10	3IN+	non-inverting input 3
11	Vss	negative supply voltage
12	4IN+	non-inverting input 4
13	4IN-	inverting input 4
14	4OUT	output 4

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Supply voltage	8 (min) 36 (max)	V
Maximum offset voltage	5	mV
Gain bandwidth	4	MHz
Slew rate	13	V/µs
Voltage noise	20	nV/√Hz
Supply current (per channel)	1.8	mA

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

LF347 - Wide bandwidth quad JFET-input operational amplifier - msarnoff.org ChipDB

LF347

Wide bandwidth quad JFET-input operational amplifier


1OUT	1 •	14	4OUT
1IN-	2	13	4IN-
1IN+	3	12	4IN+
Vcc	4	11	Vss
2IN+	5	10	3IN+
2IN-	6	9	3IN-
2OUT	7	8	3OUT

Pin	Symbol	Description
1	1OUT	output 1
2	1IN-	inverting input 1
3	1IN+	non-inverting input 1
4	Vcc	positive supply voltage
5	2IN+	non-inverting input 2
6	2IN-	inverting input 2
7	2OUT	output 2
8	3OUT	output 3
9	3IN-	inverting input 3
10	3IN+	non-inverting input 3
11	Vss	negative supply voltage
12	4IN+	non-inverting input 4
13	4IN-	inverting input 4
14	4OUT	output 4

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Supply voltage	8 (min) 36 (max)	V
Maximum offset voltage	5	mV
Gain bandwidth	4	MHz
Slew rate	13	V/µs
Voltage noise	20	nV/√Hz
Supply current (per channel)	1.8	mA

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

LF353 - Wide bandwidth dual JFET-input operational amplifier - msarnoff.org ChipDB
LF353
Wide bandwidth dual JFET-input operational amplifier

1OUT 1 • 8 Vcc
1IN- 2 7 2OUT
1IN+ 3 6 2IN-
Vss 4 5 2IN+

Pin Symbol Description
1 1OUT output 1
2 1IN- inverting input 1
3 1IN+ non-inverting input 1
4 Vss negative supply voltage
5 2IN+ non-inverting input 2
6 2IN- inverting input 2
7 2OUT output 2
8 Vcc positive supply voltage
Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Supply voltage 10 (min)
36 (max) V
Offset voltage 10 mV
Gain bandwidth 4 MHz
Slew rate 13 V/µs
Settling time to 0.01% 2 µs
Voltage noise 25 nV/√Hz
Supply current (per channel) 1.8 mA
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.
LF411 - Low-offset, low-drift JFET-input operational amplifier - msarnoff.org ChipDB
LF411
Low-offset, low-drift JFET-input operational amplifier

BAL 1 • 8 NC
IN- 2 7 Vcc
IN+ 3 6 OUT
Vss 4 5 BAL

Pin Symbol Description
1 BAL balance
2 IN- inverting input
3 IN+ non-inverting input
4 Vss negative supply voltage
5 BAL balance
6 OUT output
7 Vcc positive supply voltage
8 NC no connection
Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Maximum supply voltage ±18 V
Offset voltage 0.5 mV
Gain bandwidth 4 MHz
Slew rate 15 V/µs
Voltage noise 25 nV/√Hz
Supply current 1.8 mA
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.
LF412 - Low-offset, low-drift dual JFET-input operational amplifier - msarnoff.org ChipDB
LF412
Low-offset, low-drift dual JFET-input operational amplifier

1OUT 1 • 8 Vcc
1IN- 2 7 2OUT
1IN+ 3 6 2IN-
Vss 4 5 2IN+

Pin Symbol Description
1 1OUT output 1
2 1IN- inverting input 1
3 1IN+ non-inverting input 1
4 Vss negative supply voltage
5 2IN+ non-inverting input 2
6 2IN- inverting input 2
7 2OUT output 2
8 Vcc positive supply voltage
Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Maximum supply voltage ±18 V
Offset voltage 1 mV
Gain bandwidth 4 MHz
Slew rate 15 V/µs
Voltage noise 25 nV/√Hz
Supply current (per channel) 1.8 mA
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

LF444 - Quad low-power JFET-input operational amplifier - msarnoff.org ChipDB

LF444

Quad low-power JFET-input operational amplifier


1OUT	1 •	14	4OUT
1IN-	2	13	4IN-
1IN+	3	12	4IN+
Vcc	4	11	Vss
2IN+	5	10	3IN+
2IN-	6	9	3IN-
2OUT	7	8	3OUT

Pin	Symbol	Description
1	1OUT	output 1
2	1IN-	inverting input 1
3	1IN+	non-inverting input 1
4	Vcc	positive supply voltage
5	2IN+	non-inverting input 2
6	2IN-	inverting input 2
7	2OUT	output 2
8	3OUT	output 3
9	3IN-	inverting input 3
10	3IN+	non-inverting input 3
11	Vss	negative supply voltage
12	4IN+	non-inverting input 4
13	4IN-	inverting input 4
14	4OUT	output 4

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum supply voltage	±18	V
Offset voltage	2	mV
Gain bandwidth	1	MHz
Slew rate	1	V/µs
Voltage noise	35	nV/√Hz
Supply current (per channel)	0.15	mA

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

LM301A - Operational amplifier - msarnoff.org ChipDB

LM301A

Operational amplifier


BAL/COMP	1 •	8	COMP
IN-	2	7	Vcc
IN+	3	6	OUT
Vss	4	5	BAL

Pin	Symbol	Description
1	BAL/COMP	balance/compensation
2	IN-	inverting input
3	IN+	non-inverting input
4	Vss	negative supply voltage
5	BAL	balance
6	OUT	output
7	Vcc	positive supply voltage
8	COMP	compensation

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum supply voltage	±22 (LM101A/201A) ±18 (LM301A)	V
Minimum supply voltage	10	V
Input offset voltage	0.7 (LM101A/201A) 2 (LM301A)	mV
Gain bandwidth	1	MHz
Slew rate	0.5	V/µs
Voltage noise	15	nV/√Hz
Supply current	1.8	mA

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

LM311 - Voltage comparator - msarnoff.org ChipDB
LM311
Voltage comparator

GND 1 • 8 Vcc
IN+ 2 7 OUT
IN- 3 6 BAL/STROBE
Vss 4 5 BAL

Pin Symbol Description
1 GND ground
2 IN+ non-inverting input
3 IN- inverting input
4 Vss negative supply voltage
5 BAL balance
6 BAL/STROBE balance/strobe
7 OUT output
8 Vcc positive supply voltage
Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Maximum supply voltage 36 V
Offset voltage 3 (LM111)
7.5 (LM311) mV
Response time 200 ns
Supply current 5.1 mA
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

LM324 - Low power quad operational amplifier - msarnoff.org ChipDB

LM324

Low power quad operational amplifier


1OUT	1 •	14	4OUT
1IN-	2	13	4IN-
1IN+	3	12	4IN+
Vcc	4	11	GND
2IN+	5	10	3IN+
2IN-	6	9	3IN-
2OUT	7	8	3OUT

Pin	Symbol	Description
1	1OUT	output 1
2	1IN-	inverting input 1
3	1IN+	non-inverting input 1
4	Vcc	positive supply voltage
5	2IN+	non-inverting input 2
6	2IN-	inverting input 2
7	2OUT	output 2
8	3OUT	output 3
9	3IN-	inverting input 3
10	3IN+	non-inverting input 3
11	GND	ground/negative supply voltage
12	4IN+	non-inverting input 4
13	4IN-	inverting input 4
14	4OUT	output 4

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum supply voltage	32	V
Minimum supply voltage	3	V
Offset voltage	2	mV
Gain bandwidth	1	MHz
Slew rate	0.5	V/µs
Voltage noise	40	nV/√Hz
Supply current (per channel)	0.18	mA

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

LM348 - Quad 741 operational amplifier - msarnoff.org ChipDB

LM348

Quad 741 operational amplifier


1OUT	1 •	14	4OUT
1IN-	2	13	4IN-
1IN+	3	12	4IN+
Vcc	4	11	Vss
2IN+	5	10	3IN+
2IN-	6	9	3IN-
2OUT	7	8	3OUT

Pin	Symbol	Description
1	1OUT	output 1
2	1IN-	inverting input 1
3	1IN+	non-inverting input 1
4	Vcc	positive supply voltage
5	2IN+	non-inverting input 2
6	2IN-	inverting input 2
7	2OUT	output 2
8	3OUT	output 3
9	3IN-	inverting input 3
10	3IN+	non-inverting input 3
11	Vss	negative supply voltage
12	4IN+	non-inverting input 4
13	4IN-	inverting input 4
14	4OUT	output 4

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum supply voltage	±22 (LM148) ±18 (LM248/348)	V
Offset voltage	1	mV
Gain bandwidth	1	MHz
Slew rate	0.5	V/µs
Voltage noise	60	nV/√Hz
Supply current (per channel)	0.6	mA

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

LM358 - Low power dual operational amplifier - msarnoff.org ChipDB
LM358
Low power dual operational amplifier

1OUT 1 • 8 Vcc
1IN- 2 7 2OUT
1IN+ 3 6 2IN-
GND 4 5 2IN+

Pin Symbol Description
1 1OUT output 1
2 1IN- inverting input 1
3 1IN+ non-inverting input 1
4 GND ground
5 2IN+ non-inverting input 2
6 2IN- inverting input 1
7 2OUT output 2
8 Vcc supply voltage
Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Maximum supply voltage 32 (LM158/258/358)
26 (LM2904) V
Input offset voltage 2 mV
Unity-gain bandwidth 1 MHz
dc voltage gain 100 dB
Supply current 0.5 mA
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.
LM393 - Low-power, low-offset dual comparator - msarnoff.org ChipDB
LM393
Low-power, low-offset dual comparator

1OUT 1 • 8 Vcc
1IN- 2 7 2OUT
1IN+ 3 6 2IN-
GND 4 5 2IN+

Pin Symbol Description
1 1OUT output 1
2 1IN- inverting input 1
3 1IN+ non-inverting input 1
4 GND ground
5 2IN+ non-inverting input 2
6 2IN- inverting input 2
7 2OUT output 2
8 Vcc supply voltage
Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Maximum supply voltage 36 V
Offset voltage 1 mV
Response time 1.3 µs
Supply current 0.4 mA
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

LM301A - Operational amplifier - msarnoff.org ChipDB

LM301A

Operational amplifier


BAL/COMP	1 •	8	COMP
IN-	2	7	Vcc
IN+	3	6	OUT
Vss	4	5	BAL

Pin	Symbol	Description
1	BAL/COMP	balance/compensation
2	IN-	inverting input
3	IN+	non-inverting input
4	Vss	negative supply voltage
5	BAL	balance
6	OUT	output
7	Vcc	positive supply voltage
8	COMP	compensation

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum supply voltage	±22 (LM101A/201A) ±18 (LM301A)	V
Minimum supply voltage	10	V
Input offset voltage	0.7 (LM101A/201A) 2 (LM301A)	mV
Gain bandwidth	1	MHz
Slew rate	0.5	V/µs
Voltage noise	15	nV/√Hz
Supply current	1.8	mA

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

LM324 - Low power quad operational amplifier - msarnoff.org ChipDB

LM324

Low power quad operational amplifier


1OUT	1 •	14	4OUT
1IN-	2	13	4IN-
1IN+	3	12	4IN+
Vcc	4	11	GND
2IN+	5	10	3IN+
2IN-	6	9	3IN-
2OUT	7	8	3OUT

Pin	Symbol	Description
1	1OUT	output 1
2	1IN-	inverting input 1
3	1IN+	non-inverting input 1
4	Vcc	positive supply voltage
5	2IN+	non-inverting input 2
6	2IN-	inverting input 2
7	2OUT	output 2
8	3OUT	output 3
9	3IN-	inverting input 3
10	3IN+	non-inverting input 3
11	GND	ground/negative supply voltage
12	4IN+	non-inverting input 4
13	4IN-	inverting input 4
14	4OUT	output 4

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum supply voltage	32	V
Minimum supply voltage	3	V
Offset voltage	2	mV
Gain bandwidth	1	MHz
Slew rate	0.5	V/µs
Voltage noise	40	nV/√Hz
Supply current (per channel)	0.18	mA

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

LM348 - Quad 741 operational amplifier - msarnoff.org ChipDB

LM348

Quad 741 operational amplifier


1OUT	1 •	14	4OUT
1IN-	2	13	4IN-
1IN+	3	12	4IN+
Vcc	4	11	Vss
2IN+	5	10	3IN+
2IN-	6	9	3IN-
2OUT	7	8	3OUT

Pin	Symbol	Description
1	1OUT	output 1
2	1IN-	inverting input 1
3	1IN+	non-inverting input 1
4	Vcc	positive supply voltage
5	2IN+	non-inverting input 2
6	2IN-	inverting input 2
7	2OUT	output 2
8	3OUT	output 3
9	3IN-	inverting input 3
10	3IN+	non-inverting input 3
11	Vss	negative supply voltage
12	4IN+	non-inverting input 4
13	4IN-	inverting input 4
14	4OUT	output 4

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum supply voltage	±22 (LM148) ±18 (LM248/348)	V
Offset voltage	1	mV
Gain bandwidth	1	MHz
Slew rate	0.5	V/µs
Voltage noise	60	nV/√Hz
Supply current (per channel)	0.6	mA

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

LM358 - Low power dual operational amplifier - msarnoff.org ChipDB
LM358
Low power dual operational amplifier

1OUT 1 • 8 Vcc
1IN- 2 7 2OUT
1IN+ 3 6 2IN-
GND 4 5 2IN+

Pin Symbol Description
1 1OUT output 1
2 1IN- inverting input 1
3 1IN+ non-inverting input 1
4 GND ground
5 2IN+ non-inverting input 2
6 2IN- inverting input 1
7 2OUT output 2
8 Vcc supply voltage
Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Maximum supply voltage 32 (LM158/258/358)
26 (LM2904) V
Input offset voltage 2 mV
Unity-gain bandwidth 1 MHz
dc voltage gain 100 dB
Supply current 0.5 mA
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.
LM358 - Low power dual operational amplifier - msarnoff.org ChipDB
LM358
Low power dual operational amplifier

1OUT 1 • 8 Vcc
1IN- 2 7 2OUT
1IN+ 3 6 2IN-
GND 4 5 2IN+

Pin Symbol Description
1 1OUT output 1
2 1IN- inverting input 1
3 1IN+ non-inverting input 1
4 GND ground
5 2IN+ non-inverting input 2
6 2IN- inverting input 1
7 2OUT output 2
8 Vcc supply voltage
Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Maximum supply voltage 32 (LM158/258/358)
26 (LM2904) V
Input offset voltage 2 mV
Unity-gain bandwidth 1 MHz
dc voltage gain 100 dB
Supply current 0.5 mA
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.
LM393 - Low-power, low-offset dual comparator - msarnoff.org ChipDB
LM393
Low-power, low-offset dual comparator

1OUT 1 • 8 Vcc
1IN- 2 7 2OUT
1IN+ 3 6 2IN-
GND 4 5 2IN+

Pin Symbol Description
1 1OUT output 1
2 1IN- inverting input 1
3 1IN+ non-inverting input 1
4 GND ground
5 2IN+ non-inverting input 2
6 2IN- inverting input 2
7 2OUT output 2
8 Vcc supply voltage
Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Maximum supply voltage 36 V
Offset voltage 1 mV
Response time 1.3 µs
Supply current 0.4 mA
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

LM301A - Operational amplifier - msarnoff.org ChipDB

LM301A

Operational amplifier


BAL/COMP	1 •	8	COMP
IN-	2	7	Vcc
IN+	3	6	OUT
Vss	4	5	BAL

Pin	Symbol	Description
1	BAL/COMP	balance/compensation
2	IN-	inverting input
3	IN+	non-inverting input
4	Vss	negative supply voltage
5	BAL	balance
6	OUT	output
7	Vcc	positive supply voltage
8	COMP	compensation

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum supply voltage	±22 (LM101A/201A) ±18 (LM301A)	V
Minimum supply voltage	10	V
Input offset voltage	0.7 (LM101A/201A) 2 (LM301A)	mV
Gain bandwidth	1	MHz
Slew rate	0.5	V/µs
Voltage noise	15	nV/√Hz
Supply current	1.8	mA

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

LM311 - Voltage comparator - msarnoff.org ChipDB
LM311
Voltage comparator

GND 1 • 8 Vcc
IN+ 2 7 OUT
IN- 3 6 BAL/STROBE
Vss 4 5 BAL

Pin Symbol Description
1 GND ground
2 IN+ non-inverting input
3 IN- inverting input
4 Vss negative supply voltage
5 BAL balance
6 BAL/STROBE balance/strobe
7 OUT output
8 Vcc positive supply voltage
Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Maximum supply voltage 36 V
Offset voltage 3 (LM111)
7.5 (LM311) mV
Response time 200 ns
Supply current 5.1 mA
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

LM319 - High speed dual comparator - msarnoff.org ChipDB

LM319

High speed dual comparator


NC	1 •	14	NC
NC	2	13	NC
GND 1	3	12	OUTPUT 1
+INPUT 1	4	11	V+
-INPUT 1	5	10	-INPUT 2
V-	6	9	+INPUT 2
OUTPUT 2	7	8	GND 2

Pin	Symbol	Description
1	NC	no connection
2	NC	no connection
3	GND 1	ground 1
4	+INPUT 1	non-inverting input 1
5	-INPUT 1	inverting input 1
6	V-	negative supply voltage
7	OUTPUT 2	output 2
8	GND 2	ground 2
9	+INPUT 2	non-inverting input 2
10	-INPUT 2	inverting input 2
11	V+	positive supply voltage
12	OUTPUT 1	output 1
13	NC	not connected
14	NC	not connected

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum supply voltage	36	V
Maximum input voltage	±15	V
Input offset voltage	2	mV
Voltage gain	40	V/mV
Response time	80	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

LM324 - Low power quad operational amplifier - msarnoff.org ChipDB

LM324

Low power quad operational amplifier


1OUT	1 •	14	4OUT
1IN-	2	13	4IN-
1IN+	3	12	4IN+
Vcc	4	11	GND
2IN+	5	10	3IN+
2IN-	6	9	3IN-
2OUT	7	8	3OUT

Pin	Symbol	Description
1	1OUT	output 1
2	1IN-	inverting input 1
3	1IN+	non-inverting input 1
4	Vcc	positive supply voltage
5	2IN+	non-inverting input 2
6	2IN-	inverting input 2
7	2OUT	output 2
8	3OUT	output 3
9	3IN-	inverting input 3
10	3IN+	non-inverting input 3
11	GND	ground/negative supply voltage
12	4IN+	non-inverting input 4
13	4IN-	inverting input 4
14	4OUT	output 4

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum supply voltage	32	V
Minimum supply voltage	3	V
Offset voltage	2	mV
Gain bandwidth	1	MHz
Slew rate	0.5	V/µs
Voltage noise	40	nV/√Hz
Supply current (per channel)	0.18	mA

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

LM339 - Low-power, low-offset quad comparator - msarnoff.org ChipDB

LM339

Low-power, low-offset quad comparator


OUTPUT 2	1 •	14	OUTPUT 3
OUTPUT 1	2	13	OUTPUT 4
V+	3	12	GND
-INPUT 1	4	11	+INPUT 4
+INPUT 1	5	10	-INPUT 4
-INPUT 2	6	9	+INPUT 3
+INPUT 2	7	8	-INPUT 3

Pin	Symbol	Description
1	OUTPUT 2	output 2
2	OUTPUT 1	output 1
3	V+	positive supply voltage
4	-INPUT 1	inverting input 1
5	+INPUT 1	non-inverting input 1
6	-INPUT 2	inverting input 2
7	+INPUT 2	non-inverting input 2
8	-INPUT 3	inverting input 3
9	+INPUT 3	non-inverting input 3
10	-INPUT 4	inverting input 4
11	+INPUT 4	non-inverting input 4
12	GND	ground
13	OUTPUT 4	output 4
14	OUTPUT 3	output 3

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum supply voltage	36 or ±18	V
Maximum input voltage	36	V
Offset voltage	±3	V
Voltage gain	200	V/mV
Large signal response time	300	ns
Response time	1.3	µs

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

LM348 - Quad 741 operational amplifier - msarnoff.org ChipDB

LM348

Quad 741 operational amplifier


1OUT	1 •	14	4OUT
1IN-	2	13	4IN-
1IN+	3	12	4IN+
Vcc	4	11	Vss
2IN+	5	10	3IN+
2IN-	6	9	3IN-
2OUT	7	8	3OUT

Pin	Symbol	Description
1	1OUT	output 1
2	1IN-	inverting input 1
3	1IN+	non-inverting input 1
4	Vcc	positive supply voltage
5	2IN+	non-inverting input 2
6	2IN-	inverting input 2
7	2OUT	output 2
8	3OUT	output 3
9	3IN-	inverting input 3
10	3IN+	non-inverting input 3
11	Vss	negative supply voltage
12	4IN+	non-inverting input 4
13	4IN-	inverting input 4
14	4OUT	output 4

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum supply voltage	±22 (LM148) ±18 (LM248/348)	V
Offset voltage	1	mV
Gain bandwidth	1	MHz
Slew rate	0.5	V/µs
Voltage noise	60	nV/√Hz
Supply current (per channel)	0.6	mA

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

LM358 - Low power dual operational amplifier - msarnoff.org ChipDB
LM358
Low power dual operational amplifier

1OUT 1 • 8 Vcc
1IN- 2 7 2OUT
1IN+ 3 6 2IN-
GND 4 5 2IN+

Pin Symbol Description
1 1OUT output 1
2 1IN- inverting input 1
3 1IN+ non-inverting input 1
4 GND ground
5 2IN+ non-inverting input 2
6 2IN- inverting input 1
7 2OUT output 2
8 Vcc supply voltage
Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Maximum supply voltage 32 (LM158/258/358)
26 (LM2904) V
Input offset voltage 2 mV
Unity-gain bandwidth 1 MHz
dc voltage gain 100 dB
Supply current 0.5 mA
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

LM380 - 2.5W audio power amplifier - msarnoff.org ChipDB

LM380

2.5W audio power amplifier


BYPASS	1 •	14	Vcc
IN+	2	13	NC
GND	3	12	GND
GND	4	11	GND
GND	5	10	GND
IN-	6	9	NC
GND	7	8	OUT

Pin	Symbol	Description
1	BYPASS	bypass
2	IN+	non-inverting input
3	GND	ground (heat sink)
4	GND	ground (heat sink)
5	GND	ground (heat sink)
6	IN-	inverting input
7	GND	ground
8	OUT	output
9	NC	no connection
10	GND	ground (heat sink)
11	GND	ground (heat sink)
12	GND	ground (heat sink)
13	NC	no connection
14	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum supply voltage	22	V
Maximum peak current	1.3	A
Maximum input voltage	±0.5	V
Output power	2.5	W
Quiescent power drain	0.13	W
Bandwidth	100	kHz
Gain	50	V/V
Input impedance	150	kΩ

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

LM384 - 5W audio power amplifier - msarnoff.org ChipDB

LM384

5W audio power amplifier


BYPASS	1 •	14	Vcc
IN+	2	13	NC
GND	3	12	GND
GND	4	11	GND
GND	5	10	GND
IN-	6	9	NC
GND	7	8	OUT

Pin	Symbol	Description
1	BYPASS	bypass
2	IN+	non-inverting input
3	GND	ground (heat sink)
4	GND	ground (heat sink)
5	GND	ground (heat sink)
6	IN-	inverting input
7	GND	ground
8	OUT	output
9	NC	no connection
10	GND	ground (heat sink)
11	GND	ground (heat sink)
12	GND	ground (heat sink)
13	NC	no connection
14	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum supply voltage	26	V
Minimum supply voltage	12	V
Maximum peak current	1.3	A
Maximum input voltage	±0.5	V
Output power	5	W
Bandwidth	450	kHz
Gain	50	V/V
Input impedance	150	kΩ

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

LM386 - Low voltage audio power amplifier - msarnoff.org ChipDB
LM386
Low voltage audio power amplifier

GAIN 1 • 8 GAIN
IN- 2 7 BYPASS
IN+ 3 6 Vcc
GND 4 5 OUT

Pin Symbol Description
1 GAIN gain adjustment
2 IN- inverting input
3 IN+ non-inverting input
4 GND ground
5 OUT output
6 Vcc supply voltage
7 BYPASS bypass
8 GAIN gain adjustment
Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Supply voltage 4 (min)
12 (max) V
Quiescent current 4 mA
Output power 325 mW
Voltage gain 20 (min)
200 (max)
Bandwidth 300 kHz
Total harmonic distortion 0.2 %

Notes
The gain can be varied between 20 and 200 with a resistor in series with a capacitor across pins 1 and 8.
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.
LM393 - Low-power, low-offset dual comparator - msarnoff.org ChipDB
LM393
Low-power, low-offset dual comparator

1OUT 1 • 8 Vcc
1IN- 2 7 2OUT
1IN+ 3 6 2IN-
GND 4 5 2IN+

Pin Symbol Description
1 1OUT output 1
2 1IN- inverting input 1
3 1IN+ non-inverting input 1
4 GND ground
5 2IN+ non-inverting input 2
6 2IN- inverting input 2
7 2OUT output 2
8 Vcc supply voltage
Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Maximum supply voltage 36 V
Offset voltage 1 mV
Response time 1.3 µs
Supply current 0.4 mA
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

ICL7660 - Switched-capacitor voltage converter - msarnoff.org ChipDB

ICL7660

Switched-capacitor voltage converter


NC	1 •	8	V+
CAP+	2	7	OSC
GND	3	6	LV
CAP-	4	5	V_OUT

Pin	Symbol	Description
1	NC	no connection
2	CAP+	connection to + terminal of charge-pump capacitor
3	GND	ground
4	CAP-	connection to - terminal of charge-pump capacitor
5	V_OUT	negative voltage output
6	LV	low voltage; connect to ground for V+ < 3.5V
7	OSC	oscillator control input
8	V+	positive supply voltage (1.5V to 10V)

Notes

Basic negative voltage converter: 10µF capacitor across pins 2 and 4; 10µF capacitor across pin 5 (negative lead) and ground (positive lead).

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

MAX1771 - High-efficiency, low IQ, step-up DC-DC controller - msarnoff.org ChipDB

MAX1771

High-efficiency, low IQ, step-up DC-DC controller


EXT	1 •	8	CS
Vcc	2	7	GND
FB	3	6	AGND
SHDN	4	5	REF

Pin	Symbol	Description
1	EXT	gate drive for external n-channel power transistor
2	Vcc	supply voltage
3	FB	feedback input for adjustable output (tie to GND for fixed output)
4	SHDN	shutdown (active high)
5	REF	1.5V reference output
6	AGND	analog ground
7	GND	output driver (high-current) ground
8	CS	current sense amplifier input

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Input voltage	2 (min) 16.5 (max)	V
Output voltage (when fixed)	12	V
Maximum output power	24	W

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

MAX232 - +5V-powered multichannel RS-232 driver/receiver - msarnoff.org ChipDB

MAX232

+5V-powered multichannel RS-232 driver/receiver


C1+	1 •	16	Vcc
V+	2	15	GND
C1-	3	14	T1_OUT
C2+	4	13	R1_IN
C2-	5	12	R1_OUT
V-	6	11	T1_IN
T2_OUT	7	10	T2_IN
R2_IN	8	9	R2_OUT

Pin	Symbol	Description
1	C1+	capacitor 1 connection
2	V+	+10V output
3	C1-	capacitor 1 connection
4	C2+	capacitor 2 connection
5	C2-	capacitor 2 connection
6	V-	-10V output
7	T2_OUT	TTL/CMOS output
8	R2_IN	RS-232 input
9	R2_OUT	RS-232 output
10	T2_IN	TTL/CMOS input
11	T1_IN	TTL/CMOS input
12	R1_OUT	RS-232 output
13	R1_IN	RS-232 input
14	T1_OUT	TTL/CMOS output
15	GND	ground
16	Vcc	+5V supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Data rate	120	kbps

Notes

Use five capacitors; C1 between pins 1 and 3, C2 between pins 4 and 5, C3 between pin 2 and +5v, C4 between ground and pin 6, and C5 between +5V and ground. See datasheet for schematic.

C1 through C5 should be 1.0 µF electrolytic capacitors.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

MC34063 - Step up/down inverting switching regulator - msarnoff.org ChipDB
MC34063
Step up/down inverting switching regulator

SW C 1 • 8 DRIVER C
SW E 2 7 I_pk SENSE
CAP 3 6 Vcc
GND 4 5 COMP IN

Pin Symbol Description
1 SW C switch collector
2 SW E switch emitter
3 CAP timing capacitor
4 GND ground
5 COMP IN comparator inverting input
6 Vcc supply voltage
7 I_pk SENSE I_pk sense
8 DRIVER C driver collector
Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Supply voltage 3 (min)
40 (max) V
Output switch current 1.5 A
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

MCP23017 - 16-Bit I/O Expander with Serial Interface - msarnoff.org ChipDB

MCP23017

16-Bit I/O Expander with Serial Interface


GPB0	1 •	28	GPA7
GPB1	2	27	GPA6
GPB2	3	26	GPA5
GPB3	4	25	GPA4
GPB4	5	24	GPA3
GPB5	6	23	GPA2
GPB6	7	22	GPA1
GPB7	8	21	GPA0
V_DD	9	20	INTA
V_SS	10	19	INTB
NC	11	18	RESET
SCL	12	17	A2
SDA	13	16	A1
NC	14	15	A0

Pin	Symbol	Description
1	GPB0	Bidirectional I/O pin.
2	GPB1	Bidirectional I/O pin.
3	GPB2	Bidirectional I/O pin.
4	GPB3	Bidirectional I/O pin.
5	GPB4	Bidirectional I/O pin.
6	GPB5	Bidirectional I/O pin.
7	GPB6	Bidirectional I/O pin.
8	GPB7	Bidirectional I/O pin.
9	V_DD	Power
10	V_SS	Ground
11	NC	Not connected
12	SCL	Serial clock input
13	SDA	Serial data I/O
14	NC	Not connected
15	A0	Hardware address pin. Must be externally biased.
16	A1	Hardware address pin. Must be externally biased.
17	A2	Hardware address pin. Must be externally biased.
18	RESET	Hardware reset. Must be externally biased.
19	INTB	Interrupt output for PORTB. Can be configured as active-high, active-low or open-drain.
20	INTA	Interrupt output for PORTB. Can be configured as active-high, active-low or open-drain.
21	GPA0	Bidirectional I/O pin.
22	GPA1	Bidirectional I/O pin.
23	GPA2	Bidirectional I/O pin.
24	GPA3	Bidirectional I/O pin.
25	GPA4	Bidirectional I/O pin.
26	GPA5	Bidirectional I/O pin.
27	GPA6	Bidirectional I/O pin.
28	GPA7	Bidirectional I/O pin.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

MCP3002 - Dual channel 10-bit ADC with SPI interface - msarnoff.org ChipDB

MCP3002

Dual channel 10-bit ADC with SPI interface


CS/SHDN	1 •	8	V_CC/V_REF
CH0	2	7	CLK
CH1	3	6	D_OUT
GND	4	5	D_IN

Pin	Symbol	Description
1	CS/SHDN	chip select/shutdown
2	CH0	channel 0 analog input
3	CH1	channel 1 analog input
4	GND	ground
5	D_IN	serial data in
6	D_OUT	serial data out
7	CLK	serial clock
8	V_CC/V_REF	+2.7V to 5.5V supply/reference voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum sampling rate	200 (Vcc = 5V) 75 (Vcc = 2.7V)	ksps
Differential nonlinearity	±1	LSB
Integral nonlinearity	±1	LSB
Typical active current	375	µA

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

MCP3201 - 12-Bit A/D SPI interface A/D Converter - msarnoff.org ChipDB

MCP3201

12-Bit A/D SPI interface A/D Converter


V_Ref	1 •	8	V_DD
IN+	2	7	CLK
IN-	3	6	D_OUT
V_SS	4	5	CS/SHDN

Pin	Symbol	Description
1	V_Ref	Analog reference voltage
2	IN+	Positive analog input
3	IN-	Negative analog input
4	V_SS	Ground
5	CS/SHDN	Chip select/shutdown
6	D_OUT	SPI data out
7	CLK	SPI Clock
8	V_DD	Positive supply voltage (+2.7 to 5.5V)

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Resolution	12	bits
Maximum sample rate (V_DD = 5V)	100	ksps
Maximum sample rate (V_DD = 2.7V)	50	ksps
Minimum operating voltage	2.7	V
Maximum operating voltage (nominal)	5.5	V
Maximum operating voltage (absolute maximum rating)	7.0	V
Maximum active current (V_DD = 5V)	400	µA

Notes

Also available with 2 channels (MCP3202), 4 channels (MCP3204) and 8 channels (MCP3208)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

MCP3202 - 12-Bit 2-Channel SPI interface A/D Converter - msarnoff.org ChipDB

MCP3202

12-Bit 2-Channel SPI interface A/D Converter


CS/SHDN	1 •	8	V_DD/V_REF
CH0	2	7	CLK
CH1	3	6	D_OUT
V_SS	4	5	D_IN

Pin	Symbol	Description
1	CS/SHDN	Chip select/Shutdown
2	CH0	Channel 1 analog input
3	CH1	Channel 2 analog input
4	V_SS	Ground
5	D_IN	SPI data input
6	D_OUT	SPI data output
7	CLK	SPI clock
8	V_DD/V_REF	Supply voltage/analog reference voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Resolution	12	bits
Maximum sample rate (V_DD = 5V)	100	ksps
Maximum sample rate (V_DD = 2.7V)	50	ksps
Minimum operating voltage	2.7	V
Maximum operating voltage (nominal)	5.5	V
Maximum operating voltage (absolute maximum rating)	7.0	V
Maximum active current (V_DD = 5V)	550	µa

Notes

Also available with 1 channel (MCP3201), 4 channels (MCP3204) and 8 channels (MCP3208)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

MCP3204 - 4-channel 12 bit SPI A/D converter - msarnoff.org ChipDB

MCP3204

4-channel 12 bit SPI A/D converter


CH0	1 •	14	V_DD
CH1	2	13	V_REF
CH2	3	12	AGND
CH3	4	11	CLK
NC	5	10	D_OUT
NC	6	9	D_IN
DGND	7	8	CS/SHDN

Pin	Symbol	Description
1	CH0	Analog channel 0 input
2	CH1	Analog channel 1 input
3	CH2	Analog channel 2 input
4	CH3	Analog channel 3 input
5	NC	Not connected
6	NC	Not connected
7	DGND	Digital ground
8	CS/SHDN	Chip select / Shutdown
9	D_IN	Serial data input
10	D_OUT	Serial data output
11	CLK	SPI clock
12	AGND	Analog ground
13	V_REF	Analog reference input voltage
14	V_DD	+2.7 to 5.5 V power supply

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Max active current	400	µA
Max sampling rate	100 (5V supply) 50 (2.7V supply)	ksps
Resolution	12	bits
Conversion time	12	clock cycles

Notes

Also available as one-channel (MCP3201), two-channel (MCP3202) and eight-channel (MCP3208) version

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

NE5532 - Dual operational amplifier - msarnoff.org ChipDB
NE5532
Dual operational amplifier

1OUT 1 • 8 Vcc
1IN- 2 7 2OUT
1IN+ 3 6 2IN-
GND 4 5 2IN+

Pin Symbol Description
1 1OUT Output 1
2 1IN- Inverting input 1
3 1IN+ Non-inverting input 1
4 GND Ground
5 2IN+ Non-inverting input 2
6 2IN- Inverting input 2
7 2OUT Output 2
8 Vcc Supply voltage
Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Supply voltage ±22 V
Differential input voltage ±13 V
Input voltage Supply voltage V
Power dissipation (8-DIP) 1100 mW
Power dissipation (8-SOP) 500 mW
Operating temperature range 0~70 °C
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

PCF8574 - Remote 8-bit I/O expander for I2C bus - msarnoff.org ChipDB

PCF8574

Remote 8-bit I/O expander for I2C bus


A0	1 •	16	Vcc
A1	2	15	SDA
A2	3	14	SCL
P0	4	13	INT
P1	5	12	P7
P2	6	11	P6
P3	7	10	P5
GND	8	9	P4

Pin	Symbol	Description
1	A0	address input 0
2	A1	address input 1
3	A2	address input 2
4	P0	quasi-bidirectional I/O 0
5	P1	quasi-bidirectional I/O 1
6	P2	quasi-bidirectional I/O 2
7	P3	quasi-bidirectional I/O 3
8	GND	supply ground
9	P4	quasi-bidirectional I/O 4
10	P5	quasi-bidirectional I/O 5
11	P6	quasi-bidirectional I/O 6
12	P7	quasi-bidirectional I/O 7
13	INT	interrupt output (active LOW)
14	SCL	serial clock line
15	SDA	serial data line
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Minimum supply voltage	2.5	V
Maximum supply voltage	6.0	V
LOW level output current, minimum	10	mA
LOW level output current, typical	25	mA
HIGH level output current, minimum	10	µA
HIGH level output current, maximum	300	µA

Notes

I2C address range: 0x40-0x4e (7-bit address range: 0x20-0x27)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

PCF8574 - Remote 8-bit I/O expander for I2C bus - msarnoff.org ChipDB

PCF8574

Remote 8-bit I/O expander for I2C bus


A0	1 •	16	Vcc
A1	2	15	SDA
A2	3	14	SCL
P0	4	13	INT
P1	5	12	P7
P2	6	11	P6
P3	7	10	P5
GND	8	9	P4

Pin	Symbol	Description
1	A0	address input 0
2	A1	address input 1
3	A2	address input 2
4	P0	quasi-bidirectional I/O 0
5	P1	quasi-bidirectional I/O 1
6	P2	quasi-bidirectional I/O 2
7	P3	quasi-bidirectional I/O 3
8	GND	supply ground
9	P4	quasi-bidirectional I/O 4
10	P5	quasi-bidirectional I/O 5
11	P6	quasi-bidirectional I/O 6
12	P7	quasi-bidirectional I/O 7
13	INT	interrupt output (active LOW)
14	SCL	serial clock line
15	SDA	serial data line
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Minimum supply voltage	2.5	V
Maximum supply voltage	6.0	V
LOW level output current, minimum	10	mA
LOW level output current, typical	25	mA
HIGH level output current, minimum	10	µA
HIGH level output current, maximum	300	µA

Notes

I2C address range: 0x40-0x4e (7-bit address range: 0x20-0x27)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

PIC12F683 - 8-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology - msarnoff.org ChipDB

PIC12F683

8-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology


VDD	1 •	8	VSS
GP5/T1CKI/OSC1/CLKIN	2	7	GP0/AN0/CIN+/ICSPDAT/ULPWU
GP4/AN3/T1G/OSC2/CLKOUT	3	6	GP1/AN1/CIN-/VREF/ICSPCLK
GP3/MCLR/VPP	4	5	GP2/AN2/T0CKI/INT/COUT/CCP1

Pin	Symbol	Description
1	VDD	Positive supply
2	GP5/T1CKI/OSC1/CLKIN	GPIO 5, Timer1 clock, Crystal/Resonator, External clock input
3	GP4/AN3/T1G/OSC2/CLKOUT	GPIO 4, A/D Channel 3 input, Timer1 gate, Crystal/Resonator, FOSC/4 output
4	GP3/MCLR/VPP	GPIO 3, Master Clear, Programming voltage
5	GP2/AN2/T0CKI/INT/COUT/CCP1	GPIO 2, A/D Channel 2 input, Timer0 clock input, External Interrupt, Comparator 1 output, Capture input/Compare output/PWM output
6	GP1/AN1/CIN-/VREF/ICSPCLK	GPIO 1, A/D Channel 1 input, Comparator 1 input, External Voltage Reference, Serial Programming Clock
7	GP0/AN0/CIN+/ICSPDAT/ULPWU	GPIO 0, Comparator 1 input, Serial Programming Data I/O, Ultra Low-Power Wake-up input
8	VSS	Ground reference

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Program Memory	3.5	KB
CPU Speed	5	MIPS
RAM	128	Bytes
Data EEPROM	256	Bytes

Notes

The Low Pin-count (8) PIC® Flash microcontroller products offer all of the advantages of the well recognized mid-range x14 architecture with standardized features including a wide operating voltage of 2.0-5.5 volts, on-board EEPROM Data Memory, and nanoWatt Technology. Standard analog peripherals include up to 4 channels of 10-bit A/D, an analog comparator module with a single comparator, programmable on-chip voltage reference and a Standard Capture/Compare/PWM (CCP) module.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

PIC16F1936 - 8-Bit CMOS Microcontrollers with LCD Driver with nano Watt XLPTM Technology - msarnoff.org ChipDB

PIC16F1936

8-Bit CMOS Microcontrollers with LCD Driver with nano Watt XLPTM Technology


VPP/MCLR/RE3	1 •	28	RB7/ICSPDAT/ICDDAT/SEG13
SEG12/VCAP/SS/SRNQ/C2OUT/C12IN0-/AN0/RA0	2	27	RB6/ICSPCLK/ICDCLK/SEG14
SEG7/C12IN1-/AN1/RA1	3	26	RB5/AN13/CPS5/P2B/CCP3/P3A/T1G/COM1
COM2/DACOUT/VREF-/C2IN+/AN2/RA2	4	25	RB4/AN11/CPS4/P1D/COM0
SEG15/COM3/VREF+/C1IN+/AN3/RA3	5	24	RB3/AN9/C12IN2-/CPS3/CCP2/P2A/VLCD3
SEG4/CCP5/SRQ/T0CKI/CPS6/C1OUT/RA4	6	23	RB2/AN8/CPS2/P1B/VLCD2
SEG5/VCAP/SS/SRNQ/CPS7/C2OUT/AN4/RA5	7	22	RB1/AN10/C12IN3-/CPS1/P1C/VLCD1
GND	8	21	RB0/AN12/CPS0/CCP4/SRI/INT/SEG0
SEG2/CLKIN/OSC1/RA7	9	20	VCC
SEG1/VCAP/CLKOUT/OSC2/RA6	10	19	GND
P2B/T1CKI/T1OSO/RC0	11	18	RC7/RX/DT/P3B/SEG8
P2A/CCP2/T1OSI/RC1	12	17	RC6/TX/CK/CCP3/P3A/SEG9
SEG3/P1A/CCP1/RC2	13	16	RC5/SDO/SEG10
SEG6/SCL/SCK/RC3	14	15	RC4/SDI/SDA/T1G/SEG11

Pin	Symbol	Description
1	VPP/MCLR/RE3	Programming voltage, Master Clear, General purpose input
2	SEG12/VCAP/SS/SRNQ/C2OUT/C12IN0-/AN0/RA0	LCD Analog output, Filter capacitor, Slave Select input, SR Latch inverting output, Comparator C2 output, Comparator C1 or C2 negative input, A/D Channel 0 input, General purpose I/O
3	SEG7/C12IN1-/AN1/RA1	LCD Analog output, Comparator C1 or C2 negative input, A/D Channel 1 input, General purpose I/O
4	COM2/DACOUT/VREF-/C2IN+/AN2/RA2	LCD Analog output, Comparator Voltage Reference output, A/D Negative Voltage Reference input, Comparator C2 positive input, A/D Channel 2 input, General purpose I/O
5	SEG15/COM3/VREF+/C1IN+/AN3/RA3	LCD Analog output, LCD Analog output, A/D Voltage Reference input, Comparator C1 positive input, A/D Channel 3 input, General purpose I/O
6	SEG4/CCP5/SRQ/T0CKI/CPS6/C1OUT/RA4	LCD Analog output, Capture/Compare/PWM5, SR Latch non-inverting output, Timer0 clock input, Capacitive sensing input 6, Comparator C1 output, General purpose I/O
7	SEG5/VCAP/SS/SRNQ/CPS7/C2OUT/AN4/RA5	LCD Analog output, Filter capacitor, Slave Select input, SR Latch inverting output, Capacitive sensing input 7, Comparator C2 output, A/D Channel 4 input, General purpose I/O
8	GND	Ground reference
9	SEG2/CLKIN/OSC1/RA7	LCD Analog output, External clock input, Crystal/Resonator, General purpose I/O
10	SEG1/VCAP/CLKOUT/OSC2/RA6	LCD Analog output, Filter capacitor, FOSC/4 output, Crystal/Resonator, General purpose I/O
11	P2B/T1CKI/T1OSO/RC0	PWM output, Timer1 clock input, Timer1 oscillator connection, General purpose I/O
12	P2A/CCP2/T1OSI/RC1	PWM output, Capture/Compare/PWM2, Timer1 oscillator connection, General purpose I/O
13	SEG3/P1A/CCP1/RC2	LCD Analog output, PWM output, Capture/Compare/PWM1, General purpose I/O
14	SEG6/SCL/SCK/RC3	LCD Analog output, I2C clock, SPI clock, General purpose I/O
15	RC4/SDI/SDA/T1G/SEG11	General purpose I/O, SPI data input, I2C data input/output, Timer1 Gate input, LCD Analog output,
16	RC5/SDO/SEG10	General purpose I/O, SPI data output, LCD Analog output
17	RC6/TX/CK/CCP3/P3A/SEG9	General purpose I/O, USART asynchronous transmit, USART synchronous clock, Capture/Compare/PWM3, PWM output, LCD Analog output
18	RC7/RX/DT/P3B/SEG8	General purpose I/O, USART asynchronous input, USART synchronous data, PWM output, LCD Analog output
19	GND	Ground reference
20	VCC	Positive supply
21	RB0/AN12/CPS0/CCP4/SRI/INT/SEG0	General purpose I/O, A/D Channel 12 input, Capacitive sensing input 0, Capture/Compare/PWM4, SR Latch input, External interrupt, LCD analog output
22	RB1/AN10/C12IN3-/CPS1/P1C/VLCD1	General purpose I/O, A/D Channel 10 input, Comparator C1 or C2 negative input, Capacitive sensing input 1, PWM output, LCD analog input
23	RB2/AN8/CPS2/P1B/VLCD2	General purpose I/O, A/D Channel 8 input, Capacitive sensing input 2, PWM output
24	RB3/AN9/C12IN2-/CPS3/CCP2/P2A/VLCD3	General purpose I/O, A/D Channel 9 input, Comparator C1 or C2 negative input, Capacitive sensing input 3, Capture/Compare/PWM2, PWM output, LCD analog input
25	RB4/AN11/CPS4/P1D/COM0	General purpose I/O, A/D Channel 11 input, Capacitive sensing input 4, PWM output, LCD Analog output
26	RB5/AN13/CPS5/P2B/CCP3/P3A/T1G/COM1	General purpose I/O, A/D Channel 13 input, Capacitive sensing input 5, PWM output, Capture/Compare/PWM3, PWM output, Timer1 Gate input, LCD Analog output
27	RB6/ICSPCLK/ICDCLK/SEG14	General purpose I/O, Serial Programming Clock, In-Circuit Debug Clock, LCD Analog output
28	RB7/ICSPDAT/ICDDAT/SEG13	General purpose I/O, ICSP Data I/O, In-Circuit Data I/O, LCD Analog output

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Program Memory	14	KB
CPU Speed	8	MIPS
RAM	512	Bytes
Data EEPROM	256	Bytes

Notes

Internal 32MHz oscillator, 60 LCD segment drive support, Integrated Capacitive mTouch Sensing Module

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

PIC16F84A - PIC16F84A Microcontroller - msarnoff.org ChipDB

PIC16F84A

PIC16F84A Microcontroller


RA2	1 •	18	RA1
RA3	2	17	RA0
RA4/T0CKI	3	16	OSC1/CLKOUT
MCLR	4	15	OSC2/CLKIN
GND	5	14	Vcc
RB0/INT	6	13	RB7
RB1	7	12	RB6
RB2	8	11	RB5
RB3	9	10	RB4

Pin	Symbol	Description
1	RA2	Bi-directional I/O port
2	RA3	Bi-directional I/O port
3	RA4/T0CKI	Bi-directional I/O port
4	MCLR	Master Clear (Reset) input/programming voltage input. This pin is an active low RESET to the device.
5	GND	Ground reference for logic and I/O pins.
6	RB0/INT	External interrupt
7	RB1	Bi-directional I/O port
8	RB2	Bi-directional I/O port
9	RB3	Bi-directional I/O port
10	RB4	Interrupt-on-change pin.
11	RB5	Interrupt-on-change pin.
12	RB6	Interrupt-on-change pin, Serial programming clock
13	RB7	Interrupt-on-change pin, Serial programming data.
14	Vcc	Positive supply for logic and I/O pins.
15	OSC2/CLKIN	Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKOUT, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate.
16	OSC1/CLKOUT	Oscillator crystal input/external clock source input
17	RA0	Bi-directional I/O port
18	RA1	Bi-directional I/O port

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Max pin sink	25	mA
Max pin source	25	mA
Operating speed	20	MHz

Notes

18-pin Flash/EEPROM 8-bit Microcontroller

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

PIC18F13K50 - 20-Pin USB Flash Microcontrollers with nanoWatt XLP™ Technology - msarnoff.org ChipDB

PIC18F13K50

20-Pin USB Flash Microcontrollers with nanoWatt XLP™ Technology


VCC	1 •	20	GND
RA5/OSC1/CLKIN	2	19	RA0/D+/PGD
RA4/AN3/OSC2/CLKOUT	3	18	RA1/D-/PGC
RA3/MCLR/VPP	4	17	VUSB
RC5/CCP1/P1A/T0CKI	5	16	RC0/AN4/C12IN+/INT0/VREF+
RC4/P1B/C12OUT/SRQ	6	15	RC1/AN5/C12IN-/INT1/VREF-
RC3/AN7/P1C/C12IN3-/PGM	7	14	RC2/AN6/P1D/C12IN2-/CVREF/INT2
RC6/AN8/SS/T13CKI/T1OSCI	8	13	RB4/AN10/SDI/SDA
RC7/AN9/SDO/T1OSCO	9	12	RB5/AN11/RX/DT
RB7/TX/CK	10	11	RB6/SCK/SCI

Pin	Symbol	Description
1	VCC	Positive supply for logic and I/O pins
2	RA5/OSC1/CLKIN	Digital I/O, Oscillator crystal input or external clock input, External clock source input.
3	RA4/AN3/OSC2/CLKOUT	Digital I/O, ADC channel 3, Oscillator crystal output., In RC mode, OSC2 pin outputs CLKOUT
4	RA3/MCLR/VPP	Digital input, Active-low Master Clear with internal pull-up, High voltage programming input
5	RC5/CCP1/P1A/T0CKI	Digital I/O, Capture 1 input/Compare 1 output/PWM 1 output, Enhanced CCP1 PWM output, Timer0 external clock input
6	RC4/P1B/C12OUT/SRQ	Digital I/O, Enhanced CCP1 PWM output, Comparator C1 and C2 output, SR Latch output
7	RC3/AN7/P1C/C12IN3-/PGM	Digital I/O, ADC channel 7, Enhanced CCP1 PWM output, Comparator C1 and C2 inverting input, Low-Voltage ICSP Programming enable pin
8	RC6/AN8/SS/T13CKI/T1OSCI	Digital I/O, ADC channel 8, SPI slave select input, Timer0 and Timer3 external clock input, Timer1 oscillator input
9	RC7/AN9/SDO/T1OSCO	Digital I/O, ADC channel 9, SPI data out, Timer1 oscillator output
10	RB7/TX/CK	Digital I/O, EUSART asynchronous transmit, EUSART synchronous clock (see related RX/DT)
11	RB6/SCK/SCI	Digital I/O, Synchronous serial clock input/output for SPI mode, Synchronous serial clock input/output for I2C mode
12	RB5/AN11/RX/DT	Digital I/O, ADC channel 11, EUSART asynchronous receive, EUSART synchronous data (see related RX/TX)
13	RB4/AN10/SDI/SDA	Digital I/O, ADC channel 10, SPI data in, I2C data I/O
14	RC2/AN6/P1D/C12IN2-/CVREF/INT2	Digital I/O, ADC channel 6, Enhanced CCP1 PWM output, Comparator C1 and C2 inverting input, Comparator reference voltage output, External, interrupt 0
15	RC1/AN5/C12IN-/INT1/VREF-	Digital I/O, ADC channel 5, Comparator C1 and C2 non-inverting input, External interrupt 0, Comparator reference voltage (low) input
16	RC0/AN4/C12IN+/INT0/VREF+	Digital I/O, ADC channel 4, Comparator C1 and C2 non-inverting input, External interrupt 0, Comparator reference voltage (high) input
17	VUSB	Positive supply for USB transceiver
18	RA1/D-/PGC	Digital input, USB differential minus line (input/output), ICSP programming clock pin
19	RA0/D+/PGD	Digital input, USB differential plus line (input/output), ICSP programming data pin
20	GND	Ground reference for logic and I/O pins

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Program Memory	8	KB
CPU Speed	12	MIPS
RAM	512	Bytes
Data EEPROM	256	Bytes

Notes

High Performance PIC18 Core, USB v2.0 compliant interface

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

PIC18F13K50 - 20-Pin USB Flash Microcontrollers with nanoWatt XLP™ Technology - msarnoff.org ChipDB

PIC18F13K50

20-Pin USB Flash Microcontrollers with nanoWatt XLP™ Technology


VCC	1 •	20	GND
RA5/OSC1/CLKIN	2	19	RA0/D+/PGD
RA4/AN3/OSC2/CLKOUT	3	18	RA1/D-/PGC
RA3/MCLR/VPP	4	17	VUSB
RC5/CCP1/P1A/T0CKI	5	16	RC0/AN4/C12IN+/INT0/VREF+
RC4/P1B/C12OUT/SRQ	6	15	RC1/AN5/C12IN-/INT1/VREF-
RC3/AN7/P1C/C12IN3-/PGM	7	14	RC2/AN6/P1D/C12IN2-/CVREF/INT2
RC6/AN8/SS/T13CKI/T1OSCI	8	13	RB4/AN10/SDI/SDA
RC7/AN9/SDO/T1OSCO	9	12	RB5/AN11/RX/DT
RB7/TX/CK	10	11	RB6/SCK/SCI

Pin	Symbol	Description
1	VCC	Positive supply for logic and I/O pins
2	RA5/OSC1/CLKIN	Digital I/O, Oscillator crystal input or external clock input, External clock source input.
3	RA4/AN3/OSC2/CLKOUT	Digital I/O, ADC channel 3, Oscillator crystal output., In RC mode, OSC2 pin outputs CLKOUT
4	RA3/MCLR/VPP	Digital input, Active-low Master Clear with internal pull-up, High voltage programming input
5	RC5/CCP1/P1A/T0CKI	Digital I/O, Capture 1 input/Compare 1 output/PWM 1 output, Enhanced CCP1 PWM output, Timer0 external clock input
6	RC4/P1B/C12OUT/SRQ	Digital I/O, Enhanced CCP1 PWM output, Comparator C1 and C2 output, SR Latch output
7	RC3/AN7/P1C/C12IN3-/PGM	Digital I/O, ADC channel 7, Enhanced CCP1 PWM output, Comparator C1 and C2 inverting input, Low-Voltage ICSP Programming enable pin
8	RC6/AN8/SS/T13CKI/T1OSCI	Digital I/O, ADC channel 8, SPI slave select input, Timer0 and Timer3 external clock input, Timer1 oscillator input
9	RC7/AN9/SDO/T1OSCO	Digital I/O, ADC channel 9, SPI data out, Timer1 oscillator output
10	RB7/TX/CK	Digital I/O, EUSART asynchronous transmit, EUSART synchronous clock (see related RX/DT)
11	RB6/SCK/SCI	Digital I/O, Synchronous serial clock input/output for SPI mode, Synchronous serial clock input/output for I2C mode
12	RB5/AN11/RX/DT	Digital I/O, ADC channel 11, EUSART asynchronous receive, EUSART synchronous data (see related RX/TX)
13	RB4/AN10/SDI/SDA	Digital I/O, ADC channel 10, SPI data in, I2C data I/O
14	RC2/AN6/P1D/C12IN2-/CVREF/INT2	Digital I/O, ADC channel 6, Enhanced CCP1 PWM output, Comparator C1 and C2 inverting input, Comparator reference voltage output, External, interrupt 0
15	RC1/AN5/C12IN-/INT1/VREF-	Digital I/O, ADC channel 5, Comparator C1 and C2 non-inverting input, External interrupt 0, Comparator reference voltage (low) input
16	RC0/AN4/C12IN+/INT0/VREF+	Digital I/O, ADC channel 4, Comparator C1 and C2 non-inverting input, External interrupt 0, Comparator reference voltage (high) input
17	VUSB	Positive supply for USB transceiver
18	RA1/D-/PGC	Digital input, USB differential minus line (input/output), ICSP programming clock pin
19	RA0/D+/PGD	Digital input, USB differential plus line (input/output), ICSP programming data pin
20	GND	Ground reference for logic and I/O pins

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Program Memory	8	KB
CPU Speed	12	MIPS
RAM	512	Bytes
Data EEPROM	256	Bytes

Notes

High Performance PIC18 Core, USB v2.0 compliant interface

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

PIC18F4550 - PIC18F4550 - msarnoff.org ChipDB

PIC18F4550


MCLR/V_PP/RE3	1 •	40	RB6/KBI3/PGD
RA0/AN0	2	39	RB6/KBI2/PGC
RA1/AN1	3	38	RB5/KBI1/PGM
RA2/AN2/V_REF-/CV_REF	4	37	RB4/AN11/KBI0/CSSPP
RA3/AN3/V_REF+	5	36	RB3/AN9/CCP2/VPO
RA4/T0CKI/C1OUT/RCV	6	35	RB2/AN8/INT2/VMO
RA5/AN4/SS/HLVDIN/C2OUT	7	34	RB1/AN10/INT1/SCK/SCL
RE0/AN5/CK1SPP	8	33	RB0/AN12/INT0/FLT0/SDI/SDA
RE1/AN6/CK2SPP	9	32	V_DD
RE2/AN7/OESPP	10	31	V_SS
V_DD	11	30	RD7/SPP7/P1D
V_SS	12	29	RD6/SPP6/P1C
OSC1/CLKI	13	28	RD5/SPP5/P1B
OSC2/CLKO/RA6	14	27	RD4/SPP4
RC0/T1OSO/T13CKI	15	26	RC7/RX/DT/SDO
RC1/T1OSI/CPP2/UOE	16	25	RC6/TX/CK
RC2/CCP1/P1A	17	24	RC5/D₊/VP
V_USB	18	23	RC4/D_-/VM
RD0/SPP0	19	22	RD3/SPP3
RD1/SPP1	20	21	RD2/SPP2

Pin	Symbol	Description
1	MCLR/V_PP/RE3	.
2	RA0/AN0	.
3	RA1/AN1	.
4	RA2/AN2/V_REF-/CV_REF	.
5	RA3/AN3/V_REF+	.
6	RA4/T0CKI/C1OUT/RCV	.
7	RA5/AN4/SS/HLVDIN/C2OUT	.
8	RE0/AN5/CK1SPP	.
9	RE1/AN6/CK2SPP	.
10	RE2/AN7/OESPP	.
11	V_DD	Positive supply for logic and I/O pins.
12	V_SS	Ground reference for logic and I/O pins.
13	OSC1/CLKI	.
14	OSC2/CLKO/RA6	.
15	RC0/T1OSO/T13CKI	.
16	RC1/T1OSI/CPP2/UOE	.
17	RC2/CCP1/P1A	.
18	V_USB	Internal USB 3.3V voltage regulator.
19	RD0/SPP0	.
20	RD1/SPP1	.
21	RD2/SPP2	.
22	RD3/SPP3	.
23	RC4/D_-/VM	.
24	RC5/D₊/VP	.
25	RC6/TX/CK	.
26	RC7/RX/DT/SDO	.
27	RD4/SPP4	.
28	RD5/SPP5/P1B	.
29	RD6/SPP6/P1C	.
30	RD7/SPP7/P1D	.
31	V_SS	Ground reference for logic and I/O pins.
32	V_DD	Positive supply for logic and I/O pins.
33	RB0/AN12/INT0/FLT0/SDI/SDA	.
34	RB1/AN10/INT1/SCK/SCL	.
35	RB2/AN8/INT2/VMO	.
36	RB3/AN9/CCP2/VPO	.
37	RB4/AN11/KBI0/CSSPP	.
38	RB5/KBI1/PGM	.
39	RB6/KBI2/PGC	.
40	RB6/KBI3/PGD	.

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
(optional) parameter name	123	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

PS2501 - 4-channel optoisolator - msarnoff.org ChipDB

PS2501

4-channel optoisolator


+1	1 •	16	C1
-1	2	15	E1
+2	3	14	C2
-2	4	13	E2
+3	5	12	C3
-3	6	11	E3
+4	7	10	C4
-4	8	9	E4

Pin	Symbol	Description
1	+1	anode 1
2	-1	cathode 1
3	+2	anode 2
4	-2	cathode 2
5	+3	anode 3
6	-3	cathode 3
7	+4	anode 4
8	-4	cathode 4
9	E4	emitter 4
10	C4	collector 4
11	E3	emitter 3
12	C3	collector 3
13	E2	emitter 2
14	C2	collector 2
15	E1	emitter 1
16	C1	collector 1

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Isolation voltage	5000	Vrms
Maximum collector-emitter voltage	80	V
Switching time	3 (rising) 5 (falling)	µs

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

6581 - Sound Interface Device (SID) - msarnoff.org ChipDB

6581

Sound Interface Device (SID)


CAP1A	1 •	28	Vdd
CAP1B	2	27	AUDIO OUT
CAP2A	3	26	EXT IN
CAP2B	4	25	Vcc
RES	5	24	POTX
∅2	6	23	POTY
R/W	7	22	D7
CS	8	21	D6
A0	9	20	D5
A1	10	19	D4
A2	11	18	D3
A3	12	17	D2
A4	13	16	D1
GND	14	15	D0

Pin	Symbol	Description
1	CAP1A	capacitor C1 connection
2	CAP1B	capacitor C1 connection
3	CAP2A	capacitor C2 connection
4	CAP2B	capacitor C2 connection
5	RES	master reset
6	∅2	master clock
7	R/W	read/write select
8	CS	chip select (active low)
9	A0	address bus (register select)
10	A1	address bus (register select)
11	A2	address bus (register select)
12	A3	address bus (register select)
13	A4	address bus (register select)
14	GND	ground
15	D0	data bus
16	D1	data bus
17	D2	data bus
18	D3	data bus
19	D4	data bus
20	D5	data bus
21	D6	data bus
22	D7	data bus
23	POTY	Y-axis potentiometer input
24	POTX	X-axis potentiometer input
25	Vcc	+5VDC supply
26	EXT IN	external audio input
27	AUDIO OUT	audio output
28	Vdd	+12VDC supply

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Minimum clock cycle time	1	µs

Notes

C1 and C2 are integrating capacitors for the filter; polystyrene capacitors are preferred.

C1 and C2 should have the same value. 2200 pF gives good operation over the audio range (30Hz-12kHz).

Filter cutoff frequency is approx. 2.6×10^-5/C (where C is the value of C1 or C2).

POTX and POTY pins must be connected to RC networks; the time constant RC should be 4.7×10^-4. Recommended capacitor value is 1000 pF, recommended potentiometer value is 470 kΩ.

Maximum audio output level is approx. 3V p-p at a 6V DC level. A 1kΩ resistor should be connected from AUDIO OUT to ground, and a 1-10µF electrolytic capacitor should be used for AC coupling.

Registers:

$00	Voice 1 frequency low byte
$01	Voice 1 frequency high byte
$02	Voice 1 pulse width low byte
$03	Voice 1 pulse width high byte (bits 3-0)
$04	Voice 1 control (gate, sync, ring mod, waveform)
$05	Voice 1 attack/decay rates
$06	Voice 1 sustain level/release rate
$07	Voice 2 frequency low byte
$08	Voice 2 frequency high byte
$09	Voice 2 pulse width low byte
$0A	Voice 2 pulse width high byte (bits 3-0)
$0B	Voice 2 control (gate, sync, ring mod, waveform)
$0C	Voice 2 attack/decay rates
$0D	Voice 2 sustain level/release rate
$0E	Voice 3 frequency low byte
$0F	Voice 3 frequency high byte
$10	Voice 3 pulse width low byte
$11	Voice 3 pulse width high byte (bits 3-0)
$12	Voice 3 control (gate, sync, ring mod, waveform)
$13	Voice 3 attack/decay rates
$14	Voice 3 sustain level/release rate
$15	Filter cutoff frequency low byte
$16	Filter cutoff frequency high byte (bits 2-0)
$17	Filter resonance/control
$18	Filter mode/volume control
$19	POTX value (0-255), updated every 512 clock cycles
$1A	POTY value (0-255), updated every 512 clock cycles
$1B	Upper 8 bits of Oscillator 3 value (random number if noise waveform is selected)
$1C	Upper 8 bits of Voice 3 envelope generator value

Oscillator frequency = (Fn × Fclk/16777216) Hz

Pulse width = (PWn/40.95) %

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

SN754410 - Quadruple half-H driver - msarnoff.org ChipDB

SN754410

Quadruple half-H driver


1,2EN	1 •	16	V_CC1
1A	2	15	4A
1Y	3	14	4Y
GND	4	13	GND
GND	5	12	GND
2Y	6	11	3Y
2A	7	10	3A
V_CC2	8	9	3,4EN

Pin	Symbol	Description
1	1,2EN	enable (drivers 1 and 2)
2	1A	input 1
3	1Y	driver 1 output
4	GND	ground (heat sink)
5	GND	ground (heat sink)
6	2Y	driver 2 output
7	2A	input 2
8	V_CC2	output supply voltage
9	3,4EN	enable (drivers 3 and 4)
10	3A	input 3
11	3Y	driver 3 output
12	GND	ground (heat sink)
13	GND	ground (heat sink)
14	4Y	driver 4 output
15	4A	input 4
16	V_CC1	logic supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Supply voltage	4.5 (min) 36 (max)	V
Maximum output current per driver	1	A

Notes

When an EN line is low, the corresponding outputs assume a high-impedance off state.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

SN75468 - Seven darlington array - msarnoff.org ChipDB

SN75468

Seven darlington array


1B	1 •	16	1C
2B	2	15	2C
3B	3	14	3C
4B	4	13	4C
5B	5	12	5C
6B	6	11	6C
7B	7	10	7C
E	8	9	COM

Pin	Symbol	Description
1	1B	base 1
2	2B	base 2
3	3B	base 3
4	4B	base 4
5	5B	base 5
6	6B	base 6
7	7B	base 7
8	E	common emitter (ground)
9	COM	common
10	7C	collector 7
11	6C	collector 6
12	5C	collector 5
13	4C	collector 4
14	3C	collector 3
15	2C	collector 2
16	1C	collector 1

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Series resistance at bases	2.7 (SN75468) 10.5 (SN75469)	kΩ
Maximum collector-emitter voltage	100	V
Maximum input voltage	30	V
Maximum peak collector current	500	mA

Notes

SN75468 is designed for use with 5V TTL/CMOS devices.

SN75469 is designed for use with 6V-15V CMOS/PMOS devices.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

SN75468 - Seven darlington array - msarnoff.org ChipDB

SN75468

Seven darlington array


1B	1 •	16	1C
2B	2	15	2C
3B	3	14	3C
4B	4	13	4C
5B	5	12	5C
6B	6	11	6C
7B	7	10	7C
E	8	9	COM

Pin	Symbol	Description
1	1B	base 1
2	2B	base 2
3	3B	base 3
4	4B	base 4
5	5B	base 5
6	6B	base 6
7	7B	base 7
8	E	common emitter (ground)
9	COM	common
10	7C	collector 7
11	6C	collector 6
12	5C	collector 5
13	4C	collector 4
14	3C	collector 3
15	2C	collector 2
16	1C	collector 1

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Series resistance at bases	2.7 (SN75468) 10.5 (SN75469)	kΩ
Maximum collector-emitter voltage	100	V
Maximum input voltage	30	V
Maximum peak collector current	500	mA

Notes

SN75468 is designed for use with 5V TTL/CMOS devices.

SN75469 is designed for use with 6V-15V CMOS/PMOS devices.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

TC649 - PWM fan speed controller - msarnoff.org ChipDB

TC649

PWM fan speed controller


V_IN	1 •	8	V_DD
C_F	2	7	V_OUT
V_AS	3	6	FAULT
GND	4	5	SENSE

Pin	Symbol	Description
1	V_IN	temperature sensor; voltage range of 1.25V to 2.65V (typical)
2	C_F	positive terminal for PWM ramp generator timing capacitor; 1 µF for 30 Hz PWM
3	V_AS	auto-shutdown voltage; auto-shutdown occurs when V_IN <= V_AS
4	GND	ground
5	SENSE	fan rotation pulses; absense of pulses indicates a fault
6	FAULT	goes low to indicate a fault condition
7	V_OUT	active high complimentary output that drives the fan motor through an NPN transistor or N-channel MOSFET
8	V_DD	power supply

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
supply voltage	6	V

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

TIL311 - Hexadecimal display with logic - msarnoff.org ChipDB

TIL311

Hexadecimal display with logic


V_LED	1 •	14	Vcc
B	2	13	C
A	3	12	D
DP_L	4	11
STROBE	5	10	DP_R
	6	9
GND	7	8	BLANK

Pin	Symbol	Description
1	V_LED	LED supply voltage
2	B	Latch data input B
3	A	Latch data input A
4	DP_L	Left decimal point cathode
5	STROBE	Latch strobe input (active low)
6		no pin
7	GND	ground
8	BLANK	Display blanking input (active high)
9		no pin
10	DP_R	Right decimal point cathode
11		no pin
12	D	Latch data input D
13	C	Latch data input C
14	Vcc	Logic supply voltage

Notes

Decimal points are driven independently and current-limiting resistors (typically 1kΩ) are required.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

TL081 - JFET-input operational amplifier - msarnoff.org ChipDB

TL081

JFET-input operational amplifier


OFFSET N1	1 •	8	NC
IN-	2	7	V_CC+
IN+	3	6	OUT
V_CC-	4	5	OFFSET N2

Pin	Symbol	Description
1	OFFSET N1	offset
2	IN-	inverting input
3	IN+	non-inverting input
4	V_CC-	negative supply voltage
5	OFFSET N2	offset
6	OUT	output
7	V_CC+	positive supply voltage
8	NC	no connection

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum supply voltage	±18	V
Offset voltage	3	mV
Unity-gain bandwidth	3	MHz
Slew rate at unity gain	13	V/µs
Rise time	0.2 (TL06x) 0.1 (TL07x) 0.05 (TL08x)	µs
Overshoot factor	10 (TL061x 20 (TL07x) 20 (TL08x)	%
Equivalent input noise voltage at f = 1 kHz	42 (TL06x) 18 (TL07x) 18 (TL08x)	nV/√~Hz~
Supply current (each amplifier)	0.2 (TL06x) 1.4 (TL07x) 1.4 (TL08x)	mA

Notes

The TL06x series are low-power versions of the TL08x series.

The TL07x series are low-noise versions of the TL08x series.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

TL082 - Dual JFET-input operational amplifier - msarnoff.org ChipDB

TL082

Dual JFET-input operational amplifier


1OUT	1 •	8	V_CC+
1IN-	2	7	2OUT
1IN+	3	6	2IN-
V_CC-	4	5	2IN+

Pin	Symbol	Description
1	1OUT	output 1
2	1IN-	inverting input 1
3	1IN+	non-inverting input 1
4	V_CC-	negative supply voltage
5	2IN+	non-inverting input 2
6	2IN-	inverting input 2
7	2OUT	output 2
8	V_CC+	positive supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum supply voltage	±18	V
Offset voltage	3	mV
Unity-gain bandwidth	3	MHz
Slew rate at unity gain	13	V/µs
Rise time	0.2 (TL06x) 0.1 (TL07x) 0.05 (TL08x)	µs
Overshoot factor	10 (TL061x) 20 (TL07x) 20 (TL08x)	%
Equivalent input noise voltage at f = 1 kHz	42 (TL06x) 18 (TL07x) 18 (TL08x)	nV/√Hz
Supply current (each amplifier)	0.2 (TL06x) 1.4 (TL07x) 1.4 (TL08x)	mA

Notes

The TL06x series are low-power versions of the TL08x series.

The TL07x series are low-noise versions of the TL08x series.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

TL084 - Quad JFET-input operational amplifier - msarnoff.org ChipDB

TL084

Quad JFET-input operational amplifier


1OUT	1 •	14	4OUT
1IN-	2	13	4IN-
1IN+	3	12	4IN+
V_CC+	4	11	V_CC-
2IN+	5	10	3IN+
2IN-	6	9	3IN-
2OUT	7	8	3OUT

Pin	Symbol	Description
1	1OUT	output 1
2	1IN-	inverting input 1
3	1IN+	non-inverting input 1
4	V_CC+	positive supply voltage
5	2IN+	non-inverting input 2
6	2IN-	inverting input 2
7	2OUT	output 2
8	3OUT	output 3
9	3IN-	inverting input 3
10	3IN+	non-inverting input 3
11	V_CC-	negative supply voltage
12	4IN+	non-inverting input 4
13	4IN-	inverting input 4
14	4OUT	output 4

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum supply voltage	±18	V
Offset voltage	3	mV
Unity-gain bandwidth	3	MHz
Slew rate at unity gain	13	V/µs
Rise time	0.2 (TL06x) 0.1 (TL07x) 0.05 (TL08x)	µs
Overshoot factor	10 (TL061x 20 (TL07x) 20 (TL08x)	%
Equivalent input noise voltage at f = 1 kHz	42 (TL06x) 18 (TL07x) 18 (TL08x)	nV/√Hz
Supply current (each amplifier)	0.2 (TL06x) 1.4 (TL07x) 1.4 (TL08x)	mA

Notes

The TL06x series are low-power versions of the TL08x series.

The TL07x series are low-noise versions of the TL08x series.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

TL081 - JFET-input operational amplifier - msarnoff.org ChipDB

TL081

JFET-input operational amplifier


OFFSET N1	1 •	8	NC
IN-	2	7	V_CC+
IN+	3	6	OUT
V_CC-	4	5	OFFSET N2

Pin	Symbol	Description
1	OFFSET N1	offset
2	IN-	inverting input
3	IN+	non-inverting input
4	V_CC-	negative supply voltage
5	OFFSET N2	offset
6	OUT	output
7	V_CC+	positive supply voltage
8	NC	no connection

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum supply voltage	±18	V
Offset voltage	3	mV
Unity-gain bandwidth	3	MHz
Slew rate at unity gain	13	V/µs
Rise time	0.2 (TL06x) 0.1 (TL07x) 0.05 (TL08x)	µs
Overshoot factor	10 (TL061x 20 (TL07x) 20 (TL08x)	%
Equivalent input noise voltage at f = 1 kHz	42 (TL06x) 18 (TL07x) 18 (TL08x)	nV/√~Hz~
Supply current (each amplifier)	0.2 (TL06x) 1.4 (TL07x) 1.4 (TL08x)	mA

Notes

The TL06x series are low-power versions of the TL08x series.

The TL07x series are low-noise versions of the TL08x series.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

TL082 - Dual JFET-input operational amplifier - msarnoff.org ChipDB

TL082

Dual JFET-input operational amplifier


1OUT	1 •	8	V_CC+
1IN-	2	7	2OUT
1IN+	3	6	2IN-
V_CC-	4	5	2IN+

Pin	Symbol	Description
1	1OUT	output 1
2	1IN-	inverting input 1
3	1IN+	non-inverting input 1
4	V_CC-	negative supply voltage
5	2IN+	non-inverting input 2
6	2IN-	inverting input 2
7	2OUT	output 2
8	V_CC+	positive supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum supply voltage	±18	V
Offset voltage	3	mV
Unity-gain bandwidth	3	MHz
Slew rate at unity gain	13	V/µs
Rise time	0.2 (TL06x) 0.1 (TL07x) 0.05 (TL08x)	µs
Overshoot factor	10 (TL061x) 20 (TL07x) 20 (TL08x)	%
Equivalent input noise voltage at f = 1 kHz	42 (TL06x) 18 (TL07x) 18 (TL08x)	nV/√Hz
Supply current (each amplifier)	0.2 (TL06x) 1.4 (TL07x) 1.4 (TL08x)	mA

Notes

The TL06x series are low-power versions of the TL08x series.

The TL07x series are low-noise versions of the TL08x series.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

TL084 - Quad JFET-input operational amplifier - msarnoff.org ChipDB

TL084

Quad JFET-input operational amplifier


1OUT	1 •	14	4OUT
1IN-	2	13	4IN-
1IN+	3	12	4IN+
V_CC+	4	11	V_CC-
2IN+	5	10	3IN+
2IN-	6	9	3IN-
2OUT	7	8	3OUT

Pin	Symbol	Description
1	1OUT	output 1
2	1IN-	inverting input 1
3	1IN+	non-inverting input 1
4	V_CC+	positive supply voltage
5	2IN+	non-inverting input 2
6	2IN-	inverting input 2
7	2OUT	output 2
8	3OUT	output 3
9	3IN-	inverting input 3
10	3IN+	non-inverting input 3
11	V_CC-	negative supply voltage
12	4IN+	non-inverting input 4
13	4IN-	inverting input 4
14	4OUT	output 4

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum supply voltage	±18	V
Offset voltage	3	mV
Unity-gain bandwidth	3	MHz
Slew rate at unity gain	13	V/µs
Rise time	0.2 (TL06x) 0.1 (TL07x) 0.05 (TL08x)	µs
Overshoot factor	10 (TL061x 20 (TL07x) 20 (TL08x)	%
Equivalent input noise voltage at f = 1 kHz	42 (TL06x) 18 (TL07x) 18 (TL08x)	nV/√Hz
Supply current (each amplifier)	0.2 (TL06x) 1.4 (TL07x) 1.4 (TL08x)	mA

Notes

The TL06x series are low-power versions of the TL08x series.

The TL07x series are low-noise versions of the TL08x series.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

TL081 - JFET-input operational amplifier - msarnoff.org ChipDB

TL081

JFET-input operational amplifier


OFFSET N1	1 •	8	NC
IN-	2	7	V_CC+
IN+	3	6	OUT
V_CC-	4	5	OFFSET N2

Pin	Symbol	Description
1	OFFSET N1	offset
2	IN-	inverting input
3	IN+	non-inverting input
4	V_CC-	negative supply voltage
5	OFFSET N2	offset
6	OUT	output
7	V_CC+	positive supply voltage
8	NC	no connection

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum supply voltage	±18	V
Offset voltage	3	mV
Unity-gain bandwidth	3	MHz
Slew rate at unity gain	13	V/µs
Rise time	0.2 (TL06x) 0.1 (TL07x) 0.05 (TL08x)	µs
Overshoot factor	10 (TL061x 20 (TL07x) 20 (TL08x)	%
Equivalent input noise voltage at f = 1 kHz	42 (TL06x) 18 (TL07x) 18 (TL08x)	nV/√~Hz~
Supply current (each amplifier)	0.2 (TL06x) 1.4 (TL07x) 1.4 (TL08x)	mA

Notes

The TL06x series are low-power versions of the TL08x series.

The TL07x series are low-noise versions of the TL08x series.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

TL082 - Dual JFET-input operational amplifier - msarnoff.org ChipDB

TL082

Dual JFET-input operational amplifier


1OUT	1 •	8	V_CC+
1IN-	2	7	2OUT
1IN+	3	6	2IN-
V_CC-	4	5	2IN+

Pin	Symbol	Description
1	1OUT	output 1
2	1IN-	inverting input 1
3	1IN+	non-inverting input 1
4	V_CC-	negative supply voltage
5	2IN+	non-inverting input 2
6	2IN-	inverting input 2
7	2OUT	output 2
8	V_CC+	positive supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum supply voltage	±18	V
Offset voltage	3	mV
Unity-gain bandwidth	3	MHz
Slew rate at unity gain	13	V/µs
Rise time	0.2 (TL06x) 0.1 (TL07x) 0.05 (TL08x)	µs
Overshoot factor	10 (TL061x) 20 (TL07x) 20 (TL08x)	%
Equivalent input noise voltage at f = 1 kHz	42 (TL06x) 18 (TL07x) 18 (TL08x)	nV/√Hz
Supply current (each amplifier)	0.2 (TL06x) 1.4 (TL07x) 1.4 (TL08x)	mA

Notes

The TL06x series are low-power versions of the TL08x series.

The TL07x series are low-noise versions of the TL08x series.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

TL084 - Quad JFET-input operational amplifier - msarnoff.org ChipDB

TL084

Quad JFET-input operational amplifier


1OUT	1 •	14	4OUT
1IN-	2	13	4IN-
1IN+	3	12	4IN+
V_CC+	4	11	V_CC-
2IN+	5	10	3IN+
2IN-	6	9	3IN-
2OUT	7	8	3OUT

Pin	Symbol	Description
1	1OUT	output 1
2	1IN-	inverting input 1
3	1IN+	non-inverting input 1
4	V_CC+	positive supply voltage
5	2IN+	non-inverting input 2
6	2IN-	inverting input 2
7	2OUT	output 2
8	3OUT	output 3
9	3IN-	inverting input 3
10	3IN+	non-inverting input 3
11	V_CC-	negative supply voltage
12	4IN+	non-inverting input 4
13	4IN-	inverting input 4
14	4OUT	output 4

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum supply voltage	±18	V
Offset voltage	3	mV
Unity-gain bandwidth	3	MHz
Slew rate at unity gain	13	V/µs
Rise time	0.2 (TL06x) 0.1 (TL07x) 0.05 (TL08x)	µs
Overshoot factor	10 (TL061x 20 (TL07x) 20 (TL08x)	%
Equivalent input noise voltage at f = 1 kHz	42 (TL06x) 18 (TL07x) 18 (TL08x)	nV/√Hz
Supply current (each amplifier)	0.2 (TL06x) 1.4 (TL07x) 1.4 (TL08x)	mA

Notes

The TL06x series are low-power versions of the TL08x series.

The TL07x series are low-noise versions of the TL08x series.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

TLC272 - Precision JFET-input low-offset dual operation amplifier - msarnoff.org ChipDB

TLC272

Precision JFET-input low-offset dual operation amplifier


1OUT	1 •	8	V_DD
1IN-	2	7	2OUT
1IN+	3	6	2IN-
GND	4	5	2IN+

Pin	Symbol	Description
1	1OUT	First opamp output
2	1IN-	First opamp inverting input
3	1IN+	First opamp non-inverting input
4	GND	Ground
5	2IN+	Second opamp non-inverting input
6	2IN-	Second opamp inverting input
7	2OUT	Second opamp output
8	V_DD	Supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum offset voltage (trimmed)	500	µV
Supply voltage (absolute maximum)	18	V
Slew rate at unity gain (V_DD = 5V, V_IPP = 1V)	3.6	V/µs
Unity-gain bandwidth	1.7	MHz

Notes

Pinout LM358 compatible

Designed for high-impedance measurement applications

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

AD7528 - CMOS dual 8-bit buffered multiplying DAC - msarnoff.org ChipDB

AD7528

CMOS dual 8-bit buffered multiplying DAC


AGND	1 •	20	OUT B
OUT A	2	19	R_FB B
R_FB A	3	18	V_REF B
V_REF A	4	17	V_DD
DGND	5	16	WR
DACA/DACB	6	15	CS
(MSB) DB7	7	14	DB0 (LSB)
DB6	8	13	DB1
DB5	9	12	DB2
DB4	10	11	DB3

Pin	Symbol	Description
1	AGND	analog ground
2	OUT A	analog current output
3	R_FB A	feedback resistor connection
4	V_REF A	input reference voltage
5	DGND	digital ground
6	DACA/DACB	DAC select
7	(MSB) DB7	parallel data input
8	DB6	parallel data input
9	DB5	parallel data input
10	DB4	parallel data input
11	DB3	parallel data input
12	DB2	parallel data input
13	DB1	parallel data input
14	DB0 (LSB)	parallel data input
15	CS	chip select (active low)
16	WR	write to data register (active low)
17	V_DD	supply voltage
18	V_REF B	input reference voltage
19	R_FB B	feedback resistor connection
20	OUT B	analog current output

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Settling time, V_DD = 5V	400 (AD7528) 100 (TLC7528)	ns
Update rate, V_DD = 5V	2.5 (AD7528) 10 (TLC7528)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

TMS9918A - Video Display Processor (composite output) - msarnoff.org ChipDB

TMS9918A

Video Display Processor (composite output)


RAS	1 •	40	XTAL2
CAS	2	39	XTAL1
AD7	3	38	CPUCLK
AD6	4	37	GROMCLK
AD5	5	36	COMVID
AD4	6	35	EXTVDP
AD3	7	34	RESET/SYNC
AD2	8	33	Vcc
AD1	9	32	RD0
AD0	10	31	RD1
R/W	11	30	RD2
GND	12	29	RD3
MODE	13	28	RD4
CSW	14	27	RD5
CSR	15	26	RD6
INT	16	25	RD7
CD7	17	24	CD0
CD6	18	23	CD1
CD5	19	22	CD2
CD4	20	21	CD3

Pin	Symbol	Description
1	RAS	VRAM row address strobe
2	CAS	VRAM column address strobe
3	AD7	VRAM address/data bus (least significant bit)
4	AD6	VRAM address/data bus
5	AD5	VRAM address/data bus
6	AD4	VRAM address/data bus
7	AD3	VRAM address/data bus
8	AD2	VRAM address/data bus
9	AD1	VRAM address/data bus
10	AD0	VRAM address/data bus (most significant bit)
11	R/W	VRAM write strobe
12	GND	ground
13	MODE	CPU interface mode select (usu. a CPU address line)
14	CSW	CPU-VDP write strobe
15	CSR	CPU-VDP read strobe
16	INT	CPU interrupt output
17	CD7	CPU data bus (least significant bit)
18	CD6	CPU data bus
19	CD5	CPU data bus
20	CD4	CPU data bus
21	CD3	CPU data bus
22	CD2	CPU data bus
23	CD1	CPU data bus
24	CD0	CPU data bus (most significant bit)
25	RD7	VRAM read data bus (least significant bit)
26	RD6	VRAM read data bus
27	RD5	VRAM read data bus
28	RD4	VRAM read data bus
29	RD3	VRAM read data bus
30	RD2	VRAM read data bus
31	RD1	VRAM read data bus
32	RD0	VRAM read data bus (most significant bit)
33	Vcc	supply voltage
34	RESET/SYNC	reset (active low; when above +9V, sync input for ext. video)
35	EXTVDP	external VDP input
36	COMVID	composite video output
37	GROMCLK	VDP output clock; XTAL/24
38	CPUCLK	VDP color burst frequency clock
39	XTAL1	crystal input
40	XTAL2	crystal input

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
XTAL frequency	10.738635 ± 0.05%	MHz
XTAL load capacitors	15 (min) 39 (max)	pF
VRAM size	4 or 16	KB
Number of colors	15 plus transparent
Number of sprites	32
Sprites per line	4

Notes

Bit order numbering is backwards. 0 is the MSB and 7 is the LSB.

Write to control register: set MODE high, write data byte, write destination register in the format 10000RRR.

Write to VRAM: set MODE high, write lower address bits, write upper address bits (with highest bits set to 01), set MODE low, write data bytes. Address autoincrements.

Read from status register: set MODE high, read byte.

Read from VRAM: write lower address bits, write upper address bits (with highest bits set to 00), set MODE low, read data bytes. Address autoincrements.

MODE determines the source or destination of a CPU read/write data transfer.

Control registers:

0	VDP option control bits (mode, external VDP enable)
1	VDP option control bits (4/16K RAM, BLANK, interrupt enable, mode, sprite size, magnification)
2	Name table base address (0-15)
3	Color table base address (0-255)
4	Pattern generator base address (0-7)
5	Sprite attribute table base address (0-127)
6	Sprite pattern generator base address (0-7)
7	Text color, backdrop color

Graphics modes:

Text mode	40x24 text positions, 6x8-pixel patterns, two colors, no sprites
Graphics I mode	32x24 tile positions, 8x8-pixel patterns, 256 possible patterns with 2 colors per pattern, sprites
Graphics II mode	32x24 tile positions, 8x8-pixel patterns, 768 possible patterns with 2 colors per row, sprites
Multicolor mode	64x48 solid 4x4-pixel blocks of any color, sprites

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

TMS9928A - Video Display Processor (component output) - msarnoff.org ChipDB

TMS9928A

Video Display Processor (component output)


RAS	1 •	40	XTAL2
CAS	2	39	XTAL1
AD7	3	38	R-Y
AD6	4	37	GROMCLK
AD5	5	36	Y
AD4	6	35	B-Y
AD3	7	34	RESET/SYNC
AD2	8	33	Vcc
AD1	9	32	RD0
AD0	10	31	RD1
R/W	11	30	RD2
GND	12	29	RD3
MODE	13	28	RD4
CSW	14	27	RD5
CSR	15	26	RD6
INT	16	25	RD7
CD7	17	24	CD0
CD6	18	23	CD1
CD5	19	22	CD2
CD4	20	21	CD3

Pin	Symbol	Description
1	RAS	VRAM row address strobe
2	CAS	VRAM column address strobe
3	AD7	VRAM address/data bus (least significant bit)
4	AD6	VRAM address/data bus
5	AD5	VRAM address/data bus
6	AD4	VRAM address/data bus
7	AD3	VRAM address/data bus
8	AD2	VRAM address/data bus
9	AD1	VRAM address/data bus
10	AD0	VRAM address/data bus (most significant bit)
11	R/W	VRAM write strobe
12	GND	ground
13	MODE	CPU interface mode select (usu. a CPU address line)
14	CSW	CPU-VDP write strobe
15	CSR	CPU-VDP read strobe
16	INT	CPU interrupt output
17	CD7	CPU data bus (least significant bit)
18	CD6	CPU data bus
19	CD5	CPU data bus
20	CD4	CPU data bus
21	CD3	CPU data bus
22	CD2	CPU data bus
23	CD1	CPU data bus
24	CD0	CPU data bus (most significant bit)
25	RD7	VRAM read data bus (least significant bit)
26	RD6	VRAM read data bus
27	RD5	VRAM read data bus
28	RD4	VRAM read data bus
29	RD3	VRAM read data bus
30	RD2	VRAM read data bus
31	RD1	VRAM read data bus
32	RD0	VRAM read data bus (most significant bit)
33	Vcc	supply voltage
34	RESET/SYNC	reset (active low; when above +9V, sync input for ext. video)
35	B-Y	B-Y color difference output
36	Y	luminance/sync output
37	GROMCLK	VDP output clock; XTAL/24
38	R-Y	R-Y color difference output
39	XTAL1	crystal input
40	XTAL2	crystal input

Notes

See TMS9918A

TMS9928A outputs 60Hz video, TMS9929A outputs 50Hz video

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

TMS9928A - Video Display Processor (component output) - msarnoff.org ChipDB

TMS9928A

Video Display Processor (component output)


RAS	1 •	40	XTAL2
CAS	2	39	XTAL1
AD7	3	38	R-Y
AD6	4	37	GROMCLK
AD5	5	36	Y
AD4	6	35	B-Y
AD3	7	34	RESET/SYNC
AD2	8	33	Vcc
AD1	9	32	RD0
AD0	10	31	RD1
R/W	11	30	RD2
GND	12	29	RD3
MODE	13	28	RD4
CSW	14	27	RD5
CSR	15	26	RD6
INT	16	25	RD7
CD7	17	24	CD0
CD6	18	23	CD1
CD5	19	22	CD2
CD4	20	21	CD3

Pin	Symbol	Description
1	RAS	VRAM row address strobe
2	CAS	VRAM column address strobe
3	AD7	VRAM address/data bus (least significant bit)
4	AD6	VRAM address/data bus
5	AD5	VRAM address/data bus
6	AD4	VRAM address/data bus
7	AD3	VRAM address/data bus
8	AD2	VRAM address/data bus
9	AD1	VRAM address/data bus
10	AD0	VRAM address/data bus (most significant bit)
11	R/W	VRAM write strobe
12	GND	ground
13	MODE	CPU interface mode select (usu. a CPU address line)
14	CSW	CPU-VDP write strobe
15	CSR	CPU-VDP read strobe
16	INT	CPU interrupt output
17	CD7	CPU data bus (least significant bit)
18	CD6	CPU data bus
19	CD5	CPU data bus
20	CD4	CPU data bus
21	CD3	CPU data bus
22	CD2	CPU data bus
23	CD1	CPU data bus
24	CD0	CPU data bus (most significant bit)
25	RD7	VRAM read data bus (least significant bit)
26	RD6	VRAM read data bus
27	RD5	VRAM read data bus
28	RD4	VRAM read data bus
29	RD3	VRAM read data bus
30	RD2	VRAM read data bus
31	RD1	VRAM read data bus
32	RD0	VRAM read data bus (most significant bit)
33	Vcc	supply voltage
34	RESET/SYNC	reset (active low; when above +9V, sync input for ext. video)
35	B-Y	B-Y color difference output
36	Y	luminance/sync output
37	GROMCLK	VDP output clock; XTAL/24
38	R-Y	R-Y color difference output
39	XTAL1	crystal input
40	XTAL2	crystal input

Notes

See TMS9918A

TMS9928A outputs 60Hz video, TMS9929A outputs 50Hz video

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

TPIC6B595 - Power logic 8-bit shift register - msarnoff.org ChipDB

TPIC6B595

Power logic 8-bit shift register


NC	1 •	20	NC
Vcc	2	19	GND
SER IN	3	18	SER OUT
DRAIN0	4	17	DRAIN7
DRAIN1	5	16	DRAIN6
DRAIN2	6	15	DRAIN5
DRAIN3	7	14	DRAIN4
SRCLR	8	13	SRCK
G	9	12	RCK
GND	10	11	GND

Pin	Symbol	Description
1	NC	no connection
2	Vcc	supply voltage
3	SER IN	serial data input
4	DRAIN0	drain output
5	DRAIN1	drain output
6	DRAIN2	drain output
7	DRAIN3	drain output
8	SRCLR	clear (active low)
9	G	output enable (active low)
10	GND	ground
11	GND	ground
12	RCK	storage register latch input
13	SRCK	shift register clock input
14	DRAIN4	drain output
15	DRAIN5	drain output
16	DRAIN6	drain output
17	DRAIN7	drain output
18	SER OUT	serial data output
19	GND	ground
20	NC	no connection

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum continuous current (per output)	150	mA
Current limit (per output)	500	mA
Maximum drain-to-source voltage	50	V
Drain output rise/fall time	200	ns

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

ULN2003 - Seven darlington array - msarnoff.org ChipDB

ULN2003

Seven darlington array


1B	1 •	16	1C
2B	2	15	2C
3B	3	14	3C
4B	4	13	4C
5B	5	12	5C
6B	6	11	6C
7B	7	10	7C
E	8	9	COM

Pin	Symbol	Description
1	1B	base 1
2	2B	base 2
3	3B	base 3
4	4B	base 4
5	5B	base 5
6	6B	base 6
7	7B	base 7
8	E	common emitter (ground)
9	COM	common
10	7C	collector 7
11	6C	collector 6
12	5C	collector 5
13	4C	collector 4
14	3C	collector 3
15	2C	collector 2
16	1C	collector 1

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Series resistance at bases	n/a (ULN2002) 2.7 (ULN2003) 10.5 (ULN2004)	kΩ
Maximum collector-emitter voltage	50	V
Maximum input voltage	30	V
Maximum peak collector current	500	mA

Notes

ULN2002 is designed for use with 14V to 25V PMOS devices.

ULN2003 is designed for use with 5V TTL/CMOS devices.

ULN2004 is designed for use with 6V to 15V CMOS devices.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

ULN2003 - Seven darlington array - msarnoff.org ChipDB

ULN2003

Seven darlington array


1B	1 •	16	1C
2B	2	15	2C
3B	3	14	3C
4B	4	13	4C
5B	5	12	5C
6B	6	11	6C
7B	7	10	7C
E	8	9	COM

Pin	Symbol	Description
1	1B	base 1
2	2B	base 2
3	3B	base 3
4	4B	base 4
5	5B	base 5
6	6B	base 6
7	7B	base 7
8	E	common emitter (ground)
9	COM	common
10	7C	collector 7
11	6C	collector 6
12	5C	collector 5
13	4C	collector 4
14	3C	collector 3
15	2C	collector 2
16	1C	collector 1

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Series resistance at bases	n/a (ULN2002) 2.7 (ULN2003) 10.5 (ULN2004)	kΩ
Maximum collector-emitter voltage	50	V
Maximum input voltage	30	V
Maximum peak collector current	500	mA

Notes

ULN2002 is designed for use with 14V to 25V PMOS devices.

ULN2003 is designed for use with 5V TTL/CMOS devices.

ULN2004 is designed for use with 6V to 15V CMOS devices.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

ULN2003 - Seven darlington array - msarnoff.org ChipDB

ULN2003

Seven darlington array


1B	1 •	16	1C
2B	2	15	2C
3B	3	14	3C
4B	4	13	4C
5B	5	12	5C
6B	6	11	6C
7B	7	10	7C
E	8	9	COM

Pin	Symbol	Description
1	1B	base 1
2	2B	base 2
3	3B	base 3
4	4B	base 4
5	5B	base 5
6	6B	base 6
7	7B	base 7
8	E	common emitter (ground)
9	COM	common
10	7C	collector 7
11	6C	collector 6
12	5C	collector 5
13	4C	collector 4
14	3C	collector 3
15	2C	collector 2
16	1C	collector 1

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Series resistance at bases	n/a (ULN2002) 2.7 (ULN2003) 10.5 (ULN2004)	kΩ
Maximum collector-emitter voltage	50	V
Maximum input voltage	30	V
Maximum peak collector current	500	mA

Notes

ULN2002 is designed for use with 14V to 25V PMOS devices.

ULN2003 is designed for use with 5V TTL/CMOS devices.

ULN2004 is designed for use with 6V to 15V CMOS devices.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

ULN2803 - Eight darlington array - msarnoff.org ChipDB

ULN2803

Eight darlington array


1B	1 •	18	1C
2B	2	17	2C
3B	3	16	3C
4B	4	15	4C
5B	5	14	5C
6B	6	13	6C
7B	7	12	7C
8B	8	11	8C
GND	9	10	COM

Pin	Symbol	Description
1	1B	base 1
2	2B	base 2
3	3B	base 3
4	4B	base 4
5	5B	base 5
6	6B	base 6
7	7B	base 7
8	8B	base 8
9	GND	ground
10	COM	common
11	8C	collector 8
12	7C	collector 7
13	6C	collector 6
14	5C	collector 5
15	4C	collector 4
16	3C	collector 3
17	2C	collector 2
18	1C	collector 1

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Series resistance at bases	2.7	kΩ
Maximum collector-emitter voltage	50	V
Maximum input voltage	30	V
Maximum continuous collector current	500	mA

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

WIRE - A piece of wire - msarnoff.org ChipDB
WIRE
A piece of wire

W1 1 • 2 W2

Pin Symbol Description
1 W1 one end of the wire
2 W2 the other end of the wire

Notes
It's pretty handy for connecting stuff.Resistance is usually pretty low.It bends!
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

AY-3-8910 - Programmable sound generator - msarnoff.org ChipDB

AY-3-8910

Programmable sound generator


GND	1 •	40	Vcc
NC	2	39	TEST 1
ANALOG B	3	38	ANALOG C
ANALOG A	4	37	DA0
NC	5	36	DA1
IOB7	6	35	DA2
IOB6	7	34	DA3
IOB5	8	33	DA4
IOB4	9	32	DA5
IOB3	10	31	DA6
IOB2	11	30	DA7
IOB1	12	29	BC1
IOB0	13	28	BC2
IOA7	14	27	BDIR
IOA6	15	26	TEST 2/SEL
IOA5	16	25	A8
IOA4	17	24	A9
IOA3	18	23	RESET
IOA2	19	22	CLOCK
IOA1	20	21	IOA0

Pin	Symbol	Description
1	GND	ground
2	NC	no connection
3	ANALOG B	analog output, channel B
4	ANALOG A	analog output, channel A
5	NC	no connection
6	IOB7	I/O port B
7	IOB6	I/O port B
8	IOB5	I/O port B
9	IOB4	I/O port B
10	IOB3	I/O port B
11	IOB2	I/O port B
12	IOB1	I/O port B
13	IOB0	I/O port B
14	IOA7	I/O port A
15	IOA6	I/O port A
16	IOA5	I/O port A
17	IOA4	I/O port A
18	IOA3	I/O port A
19	IOA2	I/O port A
20	IOA1	I/O port A
21	IOA0	I/O port A
22	CLOCK	clock input
23	RESET	master reset (active low)
24	A9	chip select
25	A8	chip select
26	TEST 2/SEL	test pin (do not connect)
27	BDIR	bus direction
28	BC2	bus control
29	BC1	bus control
30	DA7	data/address bus
31	DA6	data/address bus
32	DA5	data/address bus
33	DA4	data/address bus
34	DA3	data/address bus
35	DA2	data/address bus
36	DA1	data/address bus
37	DA0	data/address bus
38	ANALOG C	analog output, channel C
39	TEST 1	test pin (do not connect)
40	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Minimum clock frequency	1	MHz
Maximum clock frequency	2.5 (AY-3-8910) 4 (YM2149)	MHz

Notes

Chip is only active when A9 is low, A8 is high, and address bits DA7-DA4 are low.

Address bits DA3-DA0 select one of the 16 control registers.

For YM2149, connecting pin 26 to ground divides CLOCK by 2.

BDIR=0, BC2=0, BC1=0: inactive, DA7-DA0 high impedance

BDIR=0, BC2=0, BC1=1: latch address, DA7-DA0 are inputs

BDIR=0, BC2=1, BC1=0: inactive, DA7-DA0 high impedance

BDIR=0, BC2=1, BC1=1: read, DA7-DA0 are outputs

BDIR=1, BC2=0, BC1=0: latch address, DA7-DA0 are inputs

BDIR=1, BC2=0, BC1=1: inactive, DA7-DA0 high impedance

BDIR=1, BC2=1, BC1=0: write, DA7-DA0 are inputs

BDIR=1, BC2=1, BC1=1: latch address, DA7-DA0 are inputs

Control registers:

$00	tone generator A frequency, low 8 bits
$01	tone generator A frequency, high 4 bits
$02	tone generator B frequency, low 8 bits
$03	tone generator B frequency, high 4 bits
$04	tone generator C frequency, low 8 bits
$05	tone generator C frequency, high 4 bits
$06	noise generator frequency, low 5 bits
$07	I/O port and mixer control
$08	channel A amplitude/envelope enable
$09	channel B amplitude/envelope enable
$0A	channel C amplitude/envelope enable
$0B	envelope frequency, low 8 bits
$0C	envelope frequency, high 8 bits
$0D	envelope shape
$0E	I/O port A data
$0F	I/O port B data

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

Z80 - Z-80 Microprocessor - msarnoff.org ChipDB

Z80

Z-80 Microprocessor


A11	1 •	40	A10
A12	2	39	A9
A13	3	38	A8
A14	4	37	A7
A15	5	36	A6
CLK	6	35	A5
D4	7	34	A4
D5	8	33	A3
D3	9	32	A2
D6	10	31	A1
Vcc	11	30	A0
D2	12	29	GND
D7	13	28	RFSH
D0	14	27	M1
D1	15	26	RESET
INT	16	25	BUSREQ
NMI	17	24	WAIT
HALT	18	23	BUSACK
MREQ	19	22	WR
IORQ	20	21	RD

Pin	Symbol	Description
1	A11	Address Line 11 Output
2	A12	Address Line 12 Output
3	A13	Address Line 13 Output
4	A14	Address Line 14 Output
5	A15	Address Line 15 Output
6	CLK	Clock Input
7	D4	Data Line 4
8	D5	Data Line 5
9	D3	Data Line 3
10	D6	Data Line 6
11	Vcc	Power +5V
12	D2	Data Line 2
13	D7	Data Line 7
14	D0	Data Line 0
15	D1	Data Line 1
16	INT	Maskable Interrupt Input (Active Low)
17	NMI	Non-Maskable Interrupt Input (Active Low)
18	HALT	Halt State Output (Active Low)
19	MREQ	Memory Request Output (Active Low)
20	IORQ	Input/Output Request Output (Active Low)
21	RD	Read Request Output (Active Low)
22	WR	Write Request Output (Active Low)
23	BUSACK	Acknowledge Bus Request for DMA Output (Active Low)
24	WAIT	Wait Request Input (Active Low)
25	BUSREQ	Bus Request Input (Active Low)
26	RESET	Reset Input (Active Low)
27	M1	Machine Cycle 1 Output (Active Low)
28	RFSH	Dynamic Memory Refresh Output (Active Low)
29	GND	Power Ground
30	A0	Address Line 1 Output
31	A1	Address Line 1 Output
32	A2	Address Line 2 Output
33	A3	Address Line 3 Output
34	A4	Address Line 4 Output
35	A5	Address Line 5 Output
36	A6	Address Line 6 Output
37	A7	Address Line 7 Output
38	A8	Address Line 8 Output
39	A9	Address Line 9 Output
40	A10	Address Line 10 Output

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum Voltage (Vcc)	6.0	V
Clock Speed (Original Z-80)	2	MHz

Notes

Registers:

A	Accumulator
F	Condition Flags
B & C	General Purpose 8-bit registers (may be used together as a 16-bit register)
D & E	General Purpose 8-bit registers (may be used together as a 16-bit register)
H & L	High & Low bytes of 16-bit Address Pointer Register
I	Interrupt Register - Holds upper 8 bits of memory address for vectored interrupt processing
R	Refresh Register - Automatically incremented for Dynamic Memory Refresh (read only)
IX & IY	16-bit Index Registers
SP	16-bit Stack Pointer Register
PC	A16-bit Program Counter Register
IFF	Interrupt Flip Flop Flag

All general-purpose registers are duplicated in the prime set (A', F',B', C', D', E', H', L')

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

Z80PIO - Z80-PIO - msarnoff.org ChipDB

Z80PIO

Z80-PIO


D2	1 •	40	D5
D7	2	39	D4
D6	3	38	D3
CE	4	37	M1
C/D	5	36	IORQ
B/A	6	35	RD
PA7	7	34	PB7
PA6	8	33	PB6
PA5	9	32	PB5
PA4	10	31	PB4
GND	11	30	PB3
PA3	12	29	PB2
PA2	13	28	PB1
PA1	14	27	PB0
PA0	15	26	+5V
ASTB	16	25	CLK
BSTB	17	24	IEI
ARDY	18	23	INT
D0	19	22	IEO
D1	20	21	BRDY

Pin	Symbol	Description
1	D2	Data Line 2 To CPU (Bi-Directional)
2	D7	Data Line 7 To CPU (Bi-Directional)
3	D6	Data Line 6 To CPU (Bi-Directional)
4	CE	Chip Enable Input (Active Low)
5	C/D	Control/Data Select (High = Ctrl, Low = Data)
6	B/A	Port A or B Select (Low = A, High = B)
7	PA7	Peripheral Port A Line 7 (Bi-Directional)
8	PA6	Peripheral Port A Line 6 (Bi-Directional)
9	PA5	Peripheral Port A Line 5 (Bi-Directional)
10	PA4	Peripheral Port A Line 4 (Bi-Directional)
11	GND	Power Ground
12	PA3	Peripheral Port A Line 3 (Bi-Directional)
13	PA2	Peripheral Port A Line 2 (Bi-Directional)
14	PA1	Peripheral Port A Line 1 (Bi-Directional)
15	PA0	Peripheral Port A Line 0 (Bi-Directional)
16	ASTB	Port A Strobe Input from Peripheral (Active Low)
17	BSTB	Port B Strobe Input from Peripherial (Active Low)
18	ARDY	Register A Ready Output (Active High)
19	D0	Data Line 0 To CPU (Bi-Directional)
20	D1	Data Line 1 To CPU (Bi-Directional)
21	BRDY	Register B Ready Output (Active High)
22	IEO	Interrupt Enable Output (Active High)
23	INT	Interrupt Input (Active Low)
24	IEI	Interrupt Enable Input (Active High)
25	CLK	System Clock Input
26	+5V	Power 5V DC
27	PB0	Peripheral Port A Line 0 (Bi-Directional)
28	PB1	Peripheral Port A Line 1 (Bi-Directional)
29	PB2	Peripheral Port A Line 2 (Bi-Directional)
30	PB3	Peripheral Port A Line 3 (Bi-Directional)
31	PB4	Peripheral Port A Line 4 (Bi-Directional)
32	PB5	Peripheral Port A Line 5 (Bi-Directional)
33	PB6	Peripheral Port A Line 6 (Bi-Directional)
34	PB7	Peripheral Port A Line 7 (Bi-Directional)
35	RD	Read Request Input from CPU (Active Low)
36	IORQ	Input/Output Request Input from CPU (Active Low)
37	M1	Machine Cycle 1 Input from CPU (Active Low)
38	D3	Data Line 3 To CPU (Bi-Directional)
39	D4	Data Line 4 To CPU (Bi-Directional)
40	D5	Data Line 5 To CPU (Bi-Directional)

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Maximum Voltage Vcc	7.0	VDC
Maximum Input Voltage	Vcc + 0.3	VDC
Storage Temperature	-65 to +150	Degrees C

Notes

The Z8O Parallel I/O (PlO) Circuit is a programmable, two port device which provides a TTL compatible interface between peripheral devices and the Z80-GPU. The CPU can configure the Z8O-PIO to interface with a wide range of peripheral devices with no other external logic required, Typical peripheral devices that are fully compatible with the Z80-PIO include most keyboards, paper tape readers and punches, printers, PROM programmers, etc. The Z8O-PIO is packaged in a 40-pin DIP, or a 44-pin PLCC, or a 44-pin OFP. NMOS and CMOS versions are also available. Major features of the Z80-PlO include.

One of the unique features of the Z80-PlO that separates it from other interface controllers is that all data transfer between the peripheral device and the CPU is accomplished under total interrupt control. The interrupt logic of the PIO permits full usage of the efficient interrupt capabilities of the Z80-CPU during I/0 transfers. All logic necessary to implement a fully nested interrupt structure is included in the PIO so that additional circuits are not required. Another unique feature of the PlO is that it can be programmed to interrupt the CPU on the occurrence of specified status conditions in the peripheral device. For example, the PlO can be programmed to interrupt if any specified peripheral alarm conditions should occur. This interrupt capability reduces the amount of time that the processor must spend in polling peripheral status.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

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About this tool

Pin	Symbol	Description
1	GND	ground
2	TRIG	trigger
3	OUT	output
4	RESET	reset (active low)
5	CV	control voltage
6	THR	threshold
7	DIS	discharge
8	Vcc	supply voltage

Parameter	Value	Unit
Maximum supply voltage	18	V
Maximum output current (NE555)	200	mA
Power dissipation	600	mW

Pin	Symbol	Description
1	N/C	no connection
2	V_F +	emitter, anode
3	V_F -	emitter, cathode
4	N/C	no connection
5	GND	supply ground
6	V_O	output
7	V_E	enable input
8	Vcc	supply voltage

Parameter	Value	Unit
Supply voltage, minimum	4.5	V
Supply voltage, maxmimum	5.5	V
Input forward voltage, typical @ 25C	1.4	V
Input forward voltage, typical @ 25C	1.4	V
Input forward voltage, max	1.8	V

Pin	Symbol	Description
1	OFFSET NULL	offset null
2	IN-	inverting input
3	IN+	non-inverting input
4	Vss	negative supply voltage
5	OFFSET NULL	offset null
6	OUT	output
7	Vcc	positive supply voltage
8	NC	no connection

Parameter	Value	Unit
Supply voltage	±10 (min) ±22 (max)	V
Maximum input voltage	±15	V
Gain bandwidth	1	MHz
Slew rate	0.5	V/µs
Supply current	1.7	mA

Pin	Symbol	Description
1	8	output 8
2	9	output 9
3	A	BCD input
4	D	BCD input
5	Vcc	supply voltage
6	B	BCD input
7	C	BCD input
8	2	output 2
9	3	output 3
10	7	output 7
11	6	output 6
12	GND	ground
13	4	output 4
14	5	output 5
15	1	output 1
16	0	output 0

Parameter	Value	Unit
Supply voltage	10 (min) 36 (max)	V
Offset voltage	10	mV
Gain bandwidth	4	MHz
Slew rate	13	V/µs
Settling time to 0.01%	2	µs
Voltage noise	25	nV/√Hz
Supply current (per channel)	1.8	mA

Parameter	Value	Unit
Maximum supply voltage	36	V
Offset voltage	3 (LM111) 7.5 (LM311)	mV
Response time	200	ns
Supply current	5.1	mA

Parameter	Value	Unit
Maximum supply voltage	32 (LM158/258/358) 26 (LM2904)	V
Input offset voltage	2	mV
Unity-gain bandwidth	1	MHz
dc voltage gain	100	dB
Supply current	0.5	mA

Pin	Symbol	Description
1	GAIN	gain adjustment
2	IN-	inverting input
3	IN+	non-inverting input
4	GND	ground
5	OUT	output
6	Vcc	supply voltage
7	BYPASS	bypass
8	GAIN	gain adjustment

Parameter	Value	Unit
Supply voltage	4 (min) 12 (max)	V
Quiescent current	4	mA
Output power	325	mW
Voltage gain	20 (min) 200 (max)
Bandwidth	300	kHz
Total harmonic distortion	0.2	%

Pin	Symbol	Description
1	SW C	switch collector
2	SW E	switch emitter
3	CAP	timing capacitor
4	GND	ground
5	COMP IN	comparator inverting input
6	Vcc	supply voltage
7	I_pk SENSE	I_pk sense
8	DRIVER C	driver collector

Parameter	Value	Unit
Supply voltage	±22	V
Differential input voltage	±13	V
Input voltage	Supply voltage	V
Power dissipation (8-DIP)	1100	mW
Power dissipation (8-SOP)	500	mW
Operating temperature range	0~70	°C

Chip DB IC Pinouts Database

16550

Universal asynchronous receiver-transmitter with FIFOs

Specifications

Notes

16550

Universal asynchronous receiver-transmitter with FIFOs

Specifications

Notes

1802

CDP1802 CMOS 8-bit microprocessor

Specifications

24LC256

256K I2C CMOS serial EEPROM

Specifications

24LC256

256K I2C CMOS serial EEPROM

Specifications

24LC256

256K I2C CMOS serial EEPROM

Specifications

28C64

8K x 8 parallel EEPROM

4001

Quad 2-input NOR gate

4002

Dual 4-input NOR gate

4011

Quad 2-input NAND gate

4013

Dual D-type flip-flop with set and clear

4014

8-bit static shift register

4015

Dual 4-bit serial-in/parallel-out shift register

4017

Decade counter/divider with 10 decoded outputs

Specifications

4020

14-stage binary counter

4021

8-bit static shift register

4023

Triple 3-input NAND gate

4024

7-stage binary ripple counter

4025

Triple 3-input NOR gate

4027

Dual J-K flip-flop with set and clear

4028

BCD to decimal decoder

Notes

4029

Synchronous 4-bit up/down binary/decade counter

4030

Quad 2-input XOR gate

4040

12-stage binary ripple counter

4046

Phase-locked loop

4047

Monostable/astable multivibrator

4049

Hex inverting buffer

4050

Hex non-inverting buffer

4051

8-channel analog multiplexer/demultiplexer

Notes

4052

Dual 4-channel analog multiplexer/demultiplexer

Notes

4053

Triple 2-channel analog multiplexer/demultiplexer (triple SPDT analog switch)

Notes

4060

14-stage ripple-carry binary counter/divider and oscillator

4066

Quad bilateral switch